Methods for forming MOS capacitors
View Patent ↗Method ( 200 ) and apparatus ( 30, 50 - 53 ) are described for MOS capacitors (MOS CAPs). The apparatus ( 30, 50 - 53 ) comprises a substrate ( 31 ) having Ohmically coupled N and P semiconductor regions ( 32, 34; 54, 56; 92, 94 ) covered by a dielectric ( 35, 57, 95 ). A conductive electrode ( 36, 58, 96 ) overlies the dielectric ( 35, 57, 95 ) above these N and P regions ( 32, 34; 54, 56; 92, 94 ). Use of the Ohmically coupled N and P regions ( 32, 34; 54, 56; 92, 94 ) substantially reduces the variation ( 40, 64, 70, 80 ) of capacitance with applied voltage associated with ordinary MOS CAPs. When these N and P regions ( 32, 34; 54, 56; 92, 94 ) have unequal doping, the capacitance variation ( 40, 64, 70, 80 ) may still be substantially compensated by adjusting the properties of the dielectric ( 57, 95 ) above the N and P regions ( 54, 56; 92, 94 ) and/or relative areas of the N and P regions ( 54, 56; 92, 94 ) or both. Accordingly, such MOS CAPS may be more easily integrated with other semiconductor devices with minimal or no disturbance to the established integrated circuit (IC) manufacturing process and without significantly increasing the occupied area beyond that required for a conventional MOS CAP.
1. A method for forming an MOS capacitor having first and second electrodes, comprising:
providing a substrate having a principal surface;
forming a first semiconductor region of a first conductivity type in or on the principal surface;
forming a second semiconductor region of a second conductivity type opposite the first conductivity type in or on the principal surface, wherein the second semiconductor region laterally surrounds the first semiconductor region;
providing a dielectric layer overlying the first and second regions;
forming a conductive layer on the dielectric layer over the first and second regions, thereby providing the first electrode of the capacitor; and
Ohmically coupling the first and second semiconductor regions, thereby providing the second electrode of the capacitor.
2. The method of claim 1 , wherein the steps of forming the first and second semiconductor regions further comprise:
forming the first semiconductor region of the first conductivity type of a first dopant concentration C 1 ; and
forming the second semiconductor region of the second conductivity type of a second dopant concentration C 2 smaller than the first dopant concentration C 1 .
3. The method of claim 2 , wherein the step of providing a dielectric layer, comprises, forming a dielectric layer having a first thickness over the first semiconductor region and a second thickness over the second semiconductor region, wherein the second thicknesses exceeds the first thickness.
4. The method of claim 1 , wherein the steps of forming the first and second semiconductor regions further comprise:
forming the first semiconductor region of the first conductivity type of a first dopant concentration C 1 and of a first lateral area A 1 under the conductive layer; and
forming the second semiconductor region of the second conductivity type of a second dopant concentration C 2 smaller than the first dopant concentration C 1 and of a second lateral area A 2 under the conductive layer larger than the first lateral area A 1 .
5. The method of claim 4 , wherein the step of providing a dielectric layer comprises, forming a dielectric layer having a first thickness over the first semiconductor region and a second thickness over the second semiconductor region, wherein the second thicknesses exceeds the first thickness.
6. The method of claim 5 , wherein the second semiconductor region has a dopant concentration C 2 and area A 2 underlying the conductive electrode, and the first semiconductor region has a dopant concentration C 1 and area A 1 underlying the conductive electrode, wherein for C 1 ≠C 2 , an area ratio A 2 /A 1 for the first and second semiconductor regions is determined based in part on a ratio [(CAPmax) 1 ]/[(CAPmax) 2 ], where (CAP max) 1 is a maximal value of a capacitance versus applied voltage curve obtained using a semiconductor region of the first conductivity type and where (CAP max) 2 is a maximal value of a capacitance versus applied voltage curve obtained using a semiconductor region of the second conductivity type, wherein a ratio [CAPmax/CAPmin] 1 for the first semiconductor region and a ratio [CAPmax/CAPmin] 2 for the second semiconductor region are substantially equal and CAPmin is a minimum value of the capacitance versus voltage curve.
7. A method for forming an MOS capacitor, comprising:
providing a substrate;
forming adjacent N and P type semiconductor regions in or on the substrate, wherein one of the N and P type semiconductor regions laterally surrounds another of the N and P type semiconductor regions;
providing a dielectric overlying the N and P type semiconductor regions;
providing a conductive electrode on the dielectric overlying the N and P type semiconductor regions;
Ohmically coupling the adjacent N and P type semiconductor regions to each other; and
providing a first capacitor connection to the conductive electrode and a second capacitor connection to the Ohmically coupled N and P semiconductor regions.
8. The method of claim 7 , wherein the step of forming adjacent N and P semiconductor regions, comprises:
implanting the N semiconductor region to a first dopant concentration C N ;
implanting the P semiconductor region to a second dopant concentration C P ; and
wherein C N and C P have a relative concentration ratio C N /C P .
9. The method of claim 8 , wherein the step of providing a dielectric, comprises:
forming a dielectric of thickness DT N over the N semiconductor region;
forming a dielectric of thickness DT P over the P semiconductor region, and wherein DT N and DT P have a relative thickness ratio DT N /DT P ≠1.
10. The method of claim 9 , wherein for C N /C P >1, then DT N /DT P <1.
11. The method of claim 7 , wherein the step of forming adjacent N and P semiconductor regions, comprises:
implanting the N semiconductor region to a first dopant concentration C N and lateral area A N ;
implanting the P semiconductor region to a second dopant concentration C P and lateral area A P ;
wherein C N and C P have a relative concentration ratio C N /C P , and A N and A P have a relative area ratio A N /A P ; and
for C N /C P >1, then A N /A P <1, and for C N /C P <1, then A N /A P >1.
12. A method for forming an MOS capacitor, comprising:
providing a substrate having a principal surface;
forming N and P semiconductor regions in or on the principal surface, wherein one of the N and P type semiconductor regions laterally surrounds another of the N and P type semiconductor regions;
forming a dielectric layer overlying the N and P semiconductor regions;
forming a conductive electrode on the dielectric layer above the N and P regions; and
Ohmically coupling the N and P semiconductor regions.
13. The method of claim 12 , wherein the dielectric layer has a first portion between the P region and the conductive electrode of a first capacitance per unit area and a second portion between the N region and the conductive electrode of a second capacitance per unit area, and wherein the first and second capacitances per unit area are different.
14. The method of claim 13 , wherein the first and second capacitances per unit area are different at least in part by differences in relative dielectric constant of the first and second portions.
15. The method of claim 13 , wherein the first and second capacitances per unit area are different at least in part by differences in relative thickness of the first and second portions.
16. The method of claim 12 , wherein the P region underlying a first portion of the dielectric layer and a first portion of the conductive electrode has a first dopant concentration C P , and the N region underlying a second portion of the dielectric layer and a second portion of the conductive electrode has a second dopant concentration C N not equal to C P .
17. The method of claim 16 , wherein the first portion of the dielectric layer has a thickness DT P and the second portion of the dielectric layer has a thickness DT N and for C N >C P , then DT P >DT N and for C N <C P , then DT P <DT N .
18. The method of claim 16 , wherein the first portion of the dielectric layer has a thickness DT P and the second portion of the dielectric layer has a thickness DT N and wherein the P region of dopant concentration C P has a first area A P underlying the conductive electrode and the N region of dopant concentration C N has a second area A N underlying the conductive electrode, and for C N >C P , then DT P >DT N and A P >A N , and for C N <C P , then DT P <DT N and A P <A N .
19. The method of claim 12 , wherein the P region has a dopant concentration C P and a first area A P underlying the conductive electrode, and the N region has a dopant concentration C N and a second area A N underlying the conductive electrode, and for C N >C P , then A P >A N , and for C N <C P , then A P <A N .
20. The method of claim 12 , wherein the P region has a dopant concentration C P and a first area A P underlying the conductive electrode, and the N region has a dopant concentration C N and a second area A N underlying the conductive electrode, wherein for C N ≠C P , an area ratio A P /A N for the N and P regions is determined based in part on a ratio [(CAPmax) N ]/[(CAPmax) P ], where (CAP max) N is a maximal value of a capacitance versus voltage curve obtained using an N-type region and where (CAP max) P is a maximal value of a capacitance versus applied voltage curve obtained using a P-type region, wherein a ratio CAPmax/CAPmin for the N-region and the P-region are substantially equal.