Method of forming device having a raised extension region
View Patent ↗A method is disclosed of forming an extension region for a transistor having a gate structure overlying a compound semiconductor layer. An anneal is used either before or after deep source/drain implantation to diffuse a dopant from a raised region adjacent the gate structure to a location underlying the gate structure. A non-diffusing activation process can be used to activate source/drain implants when the dopants from the raised region are diffused prior to deep source/drain implantation.
1. A method comprising:
forming a first gate structure overlying and abutting a first surface, the first gate structure comprising a gate dielectric and a conductive gate, wherein a material of the first surface comprises a compound semiconductor material;
forming a first sidewall spacer abutting the first gate structure;
forming an epitaxial layer on a second surface at a source/drain location associated with the first gate structure, a first portion of the epitaxial layer beginning at an outer surface of the first sidewall and a second portion of the epitaxial layer abutting the first portion and extending away from the outer surface of the first sidewall, wherein the first portion having a first average thickness, the second portion having a second average thickness greater than the first average thickness, wherein the epitaxial layer comprises a dopant that is substantially absent from a material of the second surface, the dopant having a first conductivity type.
2. The method of claim 1 wherein forming the epitaxial layer comprises forming the epitaxial layer as an in situ doped epitaxial layer including the dopant.
3. The method of claim 1 wherein forming the epitaxial layer comprises doping the epitaxial layer using an ion implantation.
4. The method of claim 1 further comprising annealing the epitaxial layer prior to implanting deep source/drain dopants.
5. The method of claim 4 further comprising activating deep source/drain implant with a substantially non-diffusing activation process.
6. The method of claim 1 wherein the compound semiconductor material comprises
at least two dissimilar group 14 semiconductor elements;
at least one group 13 and at least one group 15 semiconductor element;
at least one group 12 and at least one group 16 semiconductor element; or
combination thereof.
7. The method of claim 6 wherein the compound semiconductor material comprises at least one of carbon and germanium.
8. The method of claim 7 wherein the compound semiconductor material comprises silicon and a ratio of germanium to total atoms in the material forming the first surface is in a range of approximately 1:2-8.
9. The method of claim 1 wherein forming the first gate structure further comprises forming the first gate structure aligned on the first surface in one of a <110> direction and a <100> direction.
10. The method of claim 1 wherein the first average thickness of is in the range of approximately 10-50 nm.
11. The method of claim 1 wherein the first average thickness is approximately one-half of the second average thickness.
12. The method of claim 1 wherein the first average thickness is in the range of approximately 15-25 nm.
13. The method of claim 1 wherein the first conductivity type is a P-type conductivity.
14. The method of claim 1 wherein the first conductivity type is a N-type conductivity.
15. The method of claim 1 further comprising diffusing dopants from the epitaxial layer to a region underlying the first sidewall spacer to form at least a portion of an extension region.
16. The method of claim 1 further comprising:
forming a second gate structure overlying and abutting a third surface prior to forming the epitaxial layer; and
forming a mask layer overlying the second gate structure prior to forming the epitaxial layer to prevent formation of the epitaxial layer at a location associated with the second gate structure.
17. The method of claim 16 wherein first gate structure overlies a channel of a first conductivity type, and the second gate structure overlies a channel of a second conductivity type, wherein the second conductivity type is opposite the first conductivity type.
18. The method of claim 1 wherein forming the first sidewall spacer comprises the first sidewall spacer having a dimension of approximately 200 angstroms or less between the first gate structure and the outer surface of the first sidewall spacer.
19. The method of claim 1 further comprising:
forming a second sidewall spacer overlying the first portion of the epitaxial layer, wherein the first sidewall spacer is between the conductive gate and the second sidewall spacer; and
implanting deep source/drain dopants at a source/drain region associated with the first gate structure, wherein a location of the deep source/drain region is based upon a location of the second sidewall spacer.
20. A method comprising:
forming a gate structure overlying a channel region comprising a compound semiconductor material, wherein the gate structure comprises a gate dielectric and conductive gate; and
forming an extension region having a plurality of dopant atoms, wherein a majority of the plurality of dopant atoms is diffused into the extension region from a material lying on and above a plane defined by an interface between the gate dielectric and the channel region.