IP Library Granted Patent US 7,338,894
Granted Patent B2
US 7,338,894 · App. 11/043,827 · Granted Mar 4, 2008

Semiconductor device having nitridated oxide layer and method therefor

View Patent ↗
Loading inventors, assignments & file history…
Monitor This Case
Get email alerts when status or documents change.
Order Certified Copies
Most orders are placed with the USPTO same day — all within 24 business hours.
Order via The Patent Place →
Pre-filled with this patent's details
Quick Facts
Patent No.
US 7,338,894
App. No.
11/043,827
Granted
Mar 4, 2008
Kind
B2
Abstract

A semiconductor device includes a substrate ( 12 ), a first insulating layer ( 14 ) over a surface of the substrate ( 12 ), a layer of nanocrystals ( 13 ) over a surface of the first insulating layer ( 14 ), a second insulating layer ( 15 ) over the layer of nanocrystals ( 13 ). A nitriding ambient is applied to the second insulating layer ( 15 ) to form a barrier to further oxidation when a third insulating layer ( 22 ) is formed over the substrate ( 12 ). The nitridation of the second insulating layer ( 15 ) prevents oxidation or shrinkage of the nanocrystals and an increase in the thickness of the first insulating layer 14 without adding complexity to the process flow for manufacturing the semiconductor device ( 10 ).

Claims (20)

1. A method for forming a semiconductor device comprising:

providing a semiconductor substrate;

forming a first insulating layer over a surface of the semiconductor substrate;

forming a layer of nanocrystals over a surface of the first insulating layer;

forming a second insulating layer over the layer of nanocrystals;

applying a nitriding ambient to the second insulating layer;

selectively removing portions of the layer of nanocrystals and the first and second insulating layers to expose the surface of the semiconductor substrate; and

forming a third insulating layer over the exposed surface of the semiconductor substrate.

2. The method of claim 1 , further comprising forming a patterned polysilicon layer over the second insulating layer, wherein the patterned polysilicon layer forms gate electrodes for a plurality of non-volatile memory cells.

3. The method of claim 2 , wherein the patterned polysilicon layer is formed over the third insulating layer to form gate electrodes for a plurality of transistors.

4. The method of claim 1 , wherein applying the nitriding ambient to the second insulating layer comprises applying the nitriding ambient using plasma nitridation.

5. The method of claim 1 , wherein applying the nitriding ambient to the second insulating layer comprises applying the nitriding ambient using thermal nitridation.

6. The method of claim 1 , wherein applying nitrogen to the second insulating layer comprises applying the nitriding ambient using ion implantation.

7. The method of claim 1 , further comprising:

forming a fourth insulating layer over the second insulating layer; and applying a second nitriding ambient to the fourth insulating layer.

8. The method of claim 1 , wherein forming the second insulating layer comprises forming the second insulating layer by forming a laminate of insulating layers.

9. The method of claim 8 , wherein applying the nitriding ambient to the second insulating layer comprises applying the nitriding ambient to each layer of the laminate of insulating layers after each layer of the laminate of insulating layers is formed.

10. The method of claim 1 , further comprising annealing the semiconductor device after applying the nitriding ambient to the second insulating layer.

11. The method of claim 1 , wherein the nitriding ambient is applied to the second insulating layer after the portions of the layer of nanocrystals are selectively removed.

12. The method of claim 1 , wherein the nitriding ambient includes one or more of ammonia, nitrous oxide, atomic nitrogen, or other nitrogen compounds.

Assignments (15)
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 11759915 AND REPLACE IT WITH APPLICATION 11759935 PREVIOUSLY RECORDED ON REEL 040925 FRAME 0001. ASSIGNOR(S) HEREBY CONFIRMS THE RELEASE OF SECURITY INTEREST. Recorded Feb 17, 2020
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP, B.V. F/K/A FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 052917/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 11759915 AND REPLACE IT WITH APPLICATION 11759935 PREVIOUSLY RECORDED ON REEL 040928 FRAME 0001. ASSIGNOR(S) HEREBY CONFIRMS THE RELEASE OF SECURITY INTEREST. Recorded Jan 17, 2020
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP B.V.
Reel/Frame 052915/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 11759915 AND REPLACE IT WITH APPLICATION 11759935 PREVIOUSLY RECORDED ON REEL 037486 FRAME 0517. ASSIGNOR(S) HEREBY CONFIRMS THE ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS. Recorded Dec 10, 2019
From: CITIBANK, N.A.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 053547/0421 →
CORRECTIVE ASSIGNMENT TO CORRECT THE TO CORRECT THE APPLICATION NO. FROM 13,883,290 TO 13,833,290 PREVIOUSLY RECORDED ON REEL 041703 FRAME 0536. ASSIGNOR(S) HEREBY CONFIRMS THE THE ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS.. Recorded Feb 20, 2019
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: SHENZHEN XINGUODU TECHNOLOGY CO., LTD.
Reel/Frame 048734/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE PATENTS 8108266 AND 8062324 AND REPLACE THEM WITH 6108266 AND 8060324 PREVIOUSLY RECORDED ON REEL 037518 FRAME 0292. ASSIGNOR(S) HEREBY CONFIRMS THE ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS. Recorded Feb 1, 2017
From: CITIBANK, N.A.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 041703/0536 →
RELEASE OF SECURITY INTEREST Recorded Nov 7, 2016
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP B.V.
Reel/Frame 040928/0001 →
RELEASE OF SECURITY INTEREST Recorded Sep 21, 2016
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP, B.V., F/K/A FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 040925/0001 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jan 25, 2016
From: FREESCALE SEMICONDUCTOR, INC.
To: NORTH STAR INNOVATIONS INC.
Reel/Frame 037567/0531 →
ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS Recorded Jan 13, 2016
From: CITIBANK, N.A.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 037518/0292 →
ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS Recorded Jan 12, 2016
From: CITIBANK, N.A.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 037486/0517 →
PATENT RELEASE Recorded Dec 21, 2015
From: CITIBANK, N.A., AS COLLATERAL AGENT
To: FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 037354/0225 →
PATENT RELEASE Recorded Dec 21, 2015
From: CITIBANK, N.A., AS COLLATERAL AGENT
To: FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 037354/0688 →
PATENT RELEASE Recorded Dec 21, 2015
From: CITIBANK, N.A., AS COLLATERAL AGENT
To: FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 037356/0143 →
PATENT RELEASE Recorded Dec 21, 2015
From: CITIBANK, N.A., AS COLLATERAL AGENT
To: FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 037356/0553 →
SECURITY AGREEMENT Recorded Nov 6, 2013
From: FREESCALE SEMICONDUCTOR, INC.
To: CITIBANK, N.A., AS NOTES COLLATERAL AGENT
Reel/Frame 031591/0266 →