Deglitch circuit
View Patent ↗A deglitch circuit capable of removing noise with low power consumption. Voltage is input to a first inverter, connected to a power supply line via a first current source and grounded via a second current source. The first inverter is grounded via a capacitor and connected to first and second transistors. The gate terminals of these transistors receive a second control voltage, which is lower than the power supply voltage, and a first control voltage, which is higher than the ground level. The second transistor is connected to the ground line via a fourth current source. First voltage is supplied to a first input terminal of the latch circuit via a second inverter. The first transistor is connected to the power supply line via a third current source. Second voltage is supplied to a second input terminal of the latch circuit via the second inverter.
1. A deglitch circuit for removing a glitch, the deglitch circuit comprising:
a first inverter connected to a power supply line, which supplies power supply voltage, via a first current source and to a ground line via a second current source, the first inverter receiving an input signal;
a capacitor connected to an output terminal of the first inverter and to the ground line;
a first transistor including a source terminal, connected to the capacitor, and a drain terminal, connected to the power supply line via a third current source having a current value smaller than that of the second current source, the first transistor being biased at a first control voltage that is higher than ground potential;
a second transistor including a source terminal, connected to the capacitor, and a drain terminal, grounded via a fourth current source having a current value smaller than that of the first current source, the second transistor being biased at a second control voltage that is lower than the power supply voltage;
a second inverter having an input connected to the source terminal of the first transistor;
a third inverter having an input connected to the drain terminal of the second transistor; and
a latch circuit for receiving outputs from the drain terminals of the first and second transistors via the second and third inverters, respectively.
2. The deglitch circuit according to claim 1 , wherein:
the first control voltage is a value approximated to voltage obtained by adding a threshold voltage of the first transistor to the ground potential within a range in which the second current source is operable; and
the second control voltage is a value approximated to voltage obtained by subtracting a threshold voltage of the second transistor from the power supply voltage within a range in which the first current source is operable.
3. The deglitch circuit according to claim 2 , wherein:
the first transistor is formed by an N-channel MOS transistor;
the second current source and the fourth current source are each formed by a pair of transistors including two series-connected N-channel MOS transistors; and
in each of the pairs of the transistors forming the second current source and the fourth current source, the transistor located at a side opposite to the ground line has a gate terminal that is common with a gate terminal of the first transistor.
4. The deglitch circuit according to claim 2 , wherein:
the second transistor is formed by a P-channel MOS transistor;
the first current source and the third current source are each formed by a pair of transistors including two series-connected P-channel MOS transistors; and
in each of the pairs of the transistors forming the first current source and the third current source, the transistor located at a side opposite to the power supply line has a gate terminal that is common with the gate terminal of the second transistor.
5. The deglitch circuit according to claim 1 , further comprising:
a first auxiliary transistor including a source terminal connected to the drain terminal of the first transistor, wherein;
the first auxiliary transistor is biased at the first control voltage and includes a drain terminal connected to a first auxiliary current source;
the second inverter includes a third transistor formed by a P-channel MOS transistor and a fourth transistor formed by an N-channel MOS transistor; and
drain terminal voltage of the first transistor is supplied to a gate terminal of the third transistor, and drain terminal voltage of the first auxiliary transistor is supplied to a gate terminal of the fourth transistor.
6. The deglitch circuit according to claim 1 , further comprising:
a second auxiliary transistor including a source terminal connected to the drain terminal of the second transistor, wherein;
the second auxiliary transistor is biased at the second control voltage and includes a drain terminal connected to a second auxiliary current source;
the third inverter includes a fifth transistor formed by a P-channel MOS transistor and a sixth transistor formed by an N-channel MOS transistor; and
drain terminal voltage of the second transistor is supplied to a gate terminal of the fifth transistor, and drain terminal voltage of the second auxiliary transistor is supplied to a gate terminal of the sixth transistor.
7. The deglitch circuit according to claim 1 , further comprising:
a first switch, arranged between the fourth current source and the ground line, for switching in accordance with a NAND output of the drain terminal voltage of the second transistor and an inverted signal of the input signal.
8. The deglitch circuit according to claim 1 , further comprising:
a second switch, arranged between the third current source and the power supply line, for switching in accordance with an AND output of the input signal and an inverted signal of the drain terminal voltage of the first transistor.