Method and a computer readable medium for performing static timing analysis of a design of an integrated circuit
View Patent ↗A method for analyzing an design of an integrated circuit, the method includes defining possible timings of signals to be provided to the integrated circuit and calculating hold violations; characterized by including a stage of determining relationships between clock events and corresponding data/control events that ideally precede the clock events, in response to the possible timing of signals; and determining hold parameters in response to the relationships. A computer readable medium having stored thereon a set of instructions, the set of instructions, when executed by a processor, cause the processor to define at least one internal delay of a designed component, characterized by causing the processor to define a cell that is characterized by multiple hold times and multiple setup values for a certain clock skew value.
1. A method comprising:
performing at a computer a static timing analysis of an integrated circuit device design, the device design including an instance of a component included at a cell library, the cell library including a lookup table determined prior to performing the static timing analysis and providing timing characteristics of an input of the component;
determining at the computer a first setup time of a signal at the input of the instance based on the static timing analysis, the first setup time relative to an arrival time at the instance of a related signal;
receiving, from the cell library, a first hold time requirement corresponding to the input, the first hold time requirement determined based on the first setup time using the lookup table, the lookup table providing a relationship between each setup time of a set of setup times and a corresponding one of a set of hold time requirements, each set corresponding to the input; and
determining at the computer whether the first hold time requirement is satisfied based on delay information provided by the static timing analysis.
2. The method of claim 1 where the relationship is responsive to a temperature parameter.
3. The method of claim 1 wherein the first setup time is determined based on static timing analysis of a first logic path corresponding to the input.
4. The method of claim 1 wherein determining the first setup time comprises identifying a latest transition time at the input prior to the arrival of the related signal.
5. The method of claim 1 further comprising correcting a first hold violation at the input in response to determining that the first hold time requirement is not satisfied.
6. The method of claim 1 wherein the relationship is nonlinear.
7. The method of claim 1 wherein the relationship is responsive to a voltage parameter.
8. The method of claim 1 further comprising:
determining at the computer a second setup time at the input of the instance based on the static timing analysis, the second setup time relative to the related signal; and
receiving, from the cell library, a second hold time requirement corresponding to the input, the second hold time requirement determined based on the second setup time using the lookup table.
9. The method of claim 8 wherein the first setup time is greater than the second setup time and the first hold time requirement is less than the second hold time requirement.
10. A tangible computer readable medium having stored thereon a set of instructions, the set of instructions, when executed by a processor, cause the processor to:
determine a latest arrival time of a first signal at an input of an instance of a component at an integrated circuit device design using static timing analysis;
determine a first setup time, the first setup time based on the latest arrival time of the first signal relative to an arrival time at the instance of a related signal;
receive from a cell library a first hold time requirement corresponding to the input, the first hold time requirement determined based on the first setup time using a lookup table, the lookup table providing a relationship between each setup time of a set of setup times and a corresponding one of a set of hold time requirements, the lookup table determined prior to performing the static timing analysis; and
determine whether the first hold time requirement is satisfied based on delay information provided by the static timing analysis.
11. The computer readable medium of claim 10 wherein determining the latest arrival time of the first signal comprises performing a static timing analysis of all logic paths corresponding to the input.
12. The computer readable medium of claim 10 wherein the relationship is nonlinear.
13. The computer readable medium of claim 10 wherein the relationship is responsive to a temperature parameter.
14. The computer readable medium of claim 10 further comprising instructions to:
determine a second setup time, the second setup time relative to the related signal; and
receive from the cell library a second hold time requirement corresponding to the input, the second hold time requirement determined based on the second setup time using the lookup table.
15. The computer readable medium of claim 14 wherein the first setup time is greater than the second setup time and the first hold time requirement is less than the second hold time requirement.
16. A method comprising:
determining using a computer timing characteristics of a component included at a component library, the timing characteristics provided using a lookup table and including:
a first hold time requirement of an input of the component based on a first setup time of a signal at the input, the first setup time relative to an arrival of a related signal at the component; and
a second hold time requirement of the input based on a second setup time of the signal at the input, the second setup time relative to the related signal and different from the first setup time;
performing, at the computer and after the determining, a static timing analysis of an integrated circuit device design, the device design including an instance of the component, the static timing analysis providing a worst-case setup time corresponding to the input of the component;
receiving from the component library a minimum hold time requirement corresponding to the input, the minimum hold time requirement determined based on the worst-case setup time using the lookup table; and
determining at the computer whether the minimum hold time requirement is satisfied based on delay information provided by the static timing analysis.
17. The method of claim 16 wherein the timing characteristics further include:
a third hold time requirement of the input of the component based on a third setup time of the signal at the input, the third setup time relative to the arrival of the related signal at the component.
18. The method of claim 16 wherein the first hold time requirement and the second hold time requirement are responsive to a temperature parameter.
19. The method of claim 16 wherein the timing characteristics are responsive to a temperature parameter.
20. The method of claim 16 wherein the first setup time is greater than the second setup time and the first hold time requirement is less than the second hold time requirement.