Granted Patent B2

US 7,870,434 · App. 12/040,221 · Granted Jan 11, 2011

Abstract

Claims (39)

1. A method, comprising:

providing an integrated circuit for being debugged by a hardware debugger external to the integrated circuit and having a processing unit for executing debug software;

providing a debug status register on the integrated circuit coupled to the processing unit and for being coupled to the hardware debugger;

updating the debug status register with hardware status flags arising from running the hardware debugger and software status flags arising from running the debug software; and

masking locations in the debug status register where the hardware status flags are located from being read by the debug software while allowing the hardware status flags and the software status flags to be read by the hardware debugger.

2. The method of claim 1 , wherein the step of updating is further characterized by the hardware status flags causing entry of a debug mode.

3. The method of claim 1 , wherein the step of providing the integrated circuit is further characterized by the integrated circuit having a port for coupling the hardware debugger to the status register.

4. The method of claim 1 , wherein step of updating is further characterized by the software status flags generating interrupts to the processing unit.

5. The method of claim 1 , further comprising suspending the running of the debug software in response to the updating of a software status flag into the status register.

6. The method of claim 5 , further comprising allowing the hardware debugger to run in response to the step of suspending the running of the debug software.

7. The method of claim 1 , wherein the step of providing the integrated circuit is further characterized by the integrated circuit having a plurality of debug resources for use by the hardware debugger and the debug software.

8. The method of claim 7 , further allocating a first portion of the debug resources for running the hardware debugger and a second portion, exclusive of the first portion, of the debug resources for running the debug software.

9. The method of claim 7 , wherein the step of updating is further characterized by the plurality of debug resources updating hardware status flags and software status flags in the status register.

10. The method of claim 1 , further comprising:

providing on the integrated circuit a plurality of debug resources usable exclusively for debug operations, wherein the debug operations comprise operations directed by the debug software executed by the integrated circuit and operations directed by the hardware debugger;

committing a first portion of the plurality of debug resources for exclusive use by the hardware debugger including a first subset of fields of the debug status register and enabling availability of a second portion of the debug resources including a second subset of fields of the debug status register for use by the debug software, wherein the second portion is exclusive of the first portion; and

contemporaneously performing operations directed by the debug software and operations directed by the hardware debugger.

11. An integrated circuit, comprising:

a processing unit for performing functions including executing debug software; and

a plurality of debug resources including a status register and a control register, wherein the control register is settable by debug hardware external from the integrated circuit to prevent portions of the status register from being read by the debug software during execution of the debug software.

12. The integrated circuit of claim 11 , further comprising a port through which the debug hardware has access to the status register.

13. The integrated circuit of claim 11 , wherein all of the status register can be read by the debug hardware.

14. The integrated circuit of claim 11 , wherein:

the status register can generate a hardware debug control signal while the processing unit is executing the debug software; and

the processing unit stops executing the debug software in response to the status register generating the hardware debug control signal.

15. The integrated circuit of claim 14 , wherein the processing unit releases control to the debug hardware in response to the hardware debug control signal.

16. A method of operating an integrated circuit, which includes a debug status register, using debug hardware external to the integrated circuit and debug software executed by the integrated circuit, comprising:

loading status flags in the debug status register in response to executing the debug software and running the debug hardware;

masking a first portion of the status flags; and

performing a read of the debug status register, wherein:

if the read is by executing the debug software, the first portion of the status flags are not read; and

if the read is by running the debug hardware, all of the status flags are read.

17. The method of claim 16 , further comprising generating an interrupt in response to a status flag loaded in the debug status register.

18. The method of claim 16 , further comprising:

generating an interrupt in response to a status flag in the debug status register that was loaded in response to executing the debug software by the processing unit; and

suspending execution of the of the debug software in response to the interrupt.

19. The method of claim 18 , wherein the integrated circuit includes debug resources usable by the debug hardware and the debug software, further comprising initiating using the debug resources with the debug hardware after the step of suspending execution of the debug software.

20. The method of claim 19 , further comprising:

allocating a first portion, selected by the debug hardware, of the debug resources to only executing the debug software and a allocating a second portion of the debug resources to only running the debug hardware.

Assignments (8)