Qualification of conditional debug instructions based on address
View Patent ↗A processor implementation supports selection of an execution mode for debug instruction instances based on respective addresses thereof in addressable memory can provide an attractive mechanism for executing debug instructions in a way that allows some instances of the instructions to operate with debug semantics while suppressing other instances by executing them with no-operation (NOP) semantics. In some embodiments, selection of operative execution semantics may be based on attributes of a memory page in which a particular debug instruction instance resides. In some embodiments, portions of an address space may be delimited (e.g., using values stored in bounding registers and addresses of particular debug instruction instances compared against the delimited portions to select appropriate execution semantics. In some embodiments, both types of evaluations may be used in selecting appropriate execution semantics for a particular debug instruction instance.
1. A method comprising:
executing code on a processor, the code including at least first and second instances of a same debug instruction; and
selecting an execution mode for individual ones of the debug instruction instances based on respective addresses thereof in memory addressable by the processor, wherein based on the respective addresses, the first debug instruction instance executes with no-operation (NOP) semantics and the second debug instruction instance executes with debug-related semantics.
2. The method of claim 1 , wherein the selecting includes:
checking a debug attribute for a memory page in which a particular instance of the debug instruction resides; and
based at least in part on the debug attribute, selecting one of the no-operation (NOP) semantics and the debug-related semantics.
3. The method of claim 2 , further comprising:
maintaining the debug attribute in connection with virtual-to-physical page mapping information.
4. The method of claim 1 , wherein the selecting includes:
comparing a memory address for a particular instance of the debug instruction with contents of one or more stores that delimit one or more respective portions of the memory; and
based at least in part on correspondence of the memory address with a delimited portion, selecting one of the no-operation (NOP) semantics and the debug-related semantics.
5. The method of claim 1 , wherein the selecting includes:
performing both a page attribute check and a comparison against delimited portions of memory; and
based on a composition of the page attribute check and delimited portion comparison, selecting one of the no-operation (NOP) semantics and the debug-related semantics.
6. The method of claim 1 ,
wherein the selecting disables otherwise operative debug-related semantics of the debug instruction.
7. The method of claim 1 ,
wherein the selecting enables otherwise latent debug-related semantics of the debug instruction.
8. The method of claim 1 , further comprising:
decoding the first debug instruction instance in accordance with the address-based selection of NOP semantics to produce a NOP instruction; and
executing the NOP instruction.
9. The method of claim 1 , wherein the debug instruction is selected from a set of instructions that include or implement functionality of one or more of:
a debug notify halt (DNH) instruction;
a breakpoint or watchpoint instruction; and
a debug exception.
10. A method of controlling debug behavior of a processor, the method comprising:
identifying first and second address-delimited portions of a memory for which instances of a debug-type instruction residing therein are to be executed by the processor with differing semantics; and
conveying a machine readable encoding consistent with the first and second address-delimited portions to storage accessible to the processor, wherein logic of the processor is selective for execution semantics based on a comparison between the conveyed address-delimited portions and respective addresses in the memory of executed instances of the debug-type instruction.
11. The method of claim 10 ,
wherein the conveying is either via an external debug interface or is based on software executable on the processor.
12. The method of claim 10 , further comprising:
executing code on the processor, the code including at least first and second instances of the debug instruction, wherein based on the conveyed address-delimited portions and respective addresses of the first and second debug instruction instances, the first debug instruction instance executes with no-operation (NOP) semantics and the second debug instruction instance executes with debug-related semantics.
13. The method of claim 10 ,
wherein the logic is responsive to either or both of a set of memory page-associated debug attributes and one or more address-delimiting debug registers of the processor.
14. An apparatus comprising:
a processor that implements an instruction set that includes a debug-type instruction; and
logic of the processor selective for a respective execution mode for respective instances of the debug-type instruction based on respective addresses thereof in memory addressable by the processor.
15. The apparatus of claim 14 , further comprising:
a memory management unit that maintains in association with page mapping information, a debug attribute for memory pages,
wherein the logic selective for execution mode is responsive, with respect to a particular instance of the debug-type instruction, to the debug attribute for the memory page on which the particular debug-type instruction instance resides.
16. The apparatus of claim 14 , further comprising:
one or more machine readable stores of the processor writable to identify respective one or more address-delimited portions of the memory,
wherein the logic selective for execution mode is responsive, with respect to a particular instance of the debug-type instruction, to a comparison between contents of the machine readable stores and a memory address at which the particular debug-type instruction instance resides.
17. The apparatus of claim 14 ,
wherein based on its respective address, a first instance of the debug-type instruction executes with no-operation (NOP) semantics, and
wherein based on its respective address, a second instance of the debug-type instruction executes with debug-related semantics.
18. The apparatus of claim 14 , further comprising:
a memory management unit that maintains in association with page mapping information, a debug attribute for memory pages; and
one or more machine readable stores of the processor writable to identify respective one or more address-delimited portions of the memory,
wherein the logic selective for execution mode is responsive, with respect to a particular instance of the debug-type instruction and its address in the memory, to a composition of both the associated debug attribute and the address-delimited portions of the memory.
19. The apparatus of claim 18 ,
wherein the composition is characterized in that both the page-associated debug attribute and one of the address-delimited portions of memory are selective for debug-related semantics.
20. The apparatus of claim 18 ,
wherein the composition is characterized in that either the page-associated debug attribute or one of the address-delimited portions of memory is selective for debug-related semantics.