Granted Patent B2

US 7,700,499 · App. 12/008,607 · Granted Apr 20, 2010

Abstract

Claims (41)

1. A method for making a semiconductor device, comprising:

providing a semiconductor structure equipped with first and second gate structures and having channel regions associated with the gate structures;

depositing a first sub-layer of a first stressor material over the gate structures and channel regions, said first stressor material containing silicon-nitrogen bonds;

curing the first stressor material through exposure to a radiation source, thereby forming a first cured sub-layer;

depositing a second sub-layer of a second stressor material over the first cured sub-layer, said second stressor material containing silicon-nitrogen bonds;

curing the second stressor material through exposure to a radiation source, thereby forming a second cured sub-layer;

depositing a third sub-layer of a third stressor material between the first and second gate structures and in contact with the second sub-layer;

curing the third stressor material through exposure to a radiation source;

depositing a fourth sub-layer of a fourth stressor material between the first and second gate structures and in contact with the third sub-layer; and

curing the fourth stressor material through exposure to radiation source.

2. The method of claim 1 , wherein the first and second stressor materials impart tensile stress to the semiconductor structure.

3. The method of claim 1 , wherein the first and second stressor materials are different.

4. The method of claim 1 , wherein the radiation source is a UV radiation source.

5. The method of claim 1 , wherein the radiation source is an e-beam radiation source.

6. The method of claim 1 , wherein the first and second sub-layers are formed by plasma enhanced chemical vapor deposition (PECVD).

7. The method of claim 1 , wherein each of the first and second sub-layers has a thickness of less than about 250 Å.

8. The method of claim 1 , wherein each of the first and second sub-layers has a thickness within the range of about 200 Å to about 250 Å.

9. The method of claim 1 , wherein the radiation source is a UV radiation source, wherein the step of curing the first stressor material involves exposure to the UV radiation source for less than about 10 minutes, and wherein the step of curing the second stressor material involves exposure to the UV radiation source for less than about 10 minutes.

10. The method of claim 1 , wherein the radiation source is a UV radiation source, and wherein each of the first and second sub-layers is cured through exposure to UV radiation for a duration of time within the range of about 5 to about 10 minutes.

11. The method of claim 1 , wherein the radiation source is a UV radiation source, wherein the semiconductor structure comprises first and second gate structures, and wherein the third sub-layer of a third stressor material is deposited between the first and second gate structures and in contact with the second sub-layer and is cured through exposure to UV radiation.

12. The method of claim 11 , wherein each of the first, second and third sub-layers has a thickness of less than about 250 Å.

13. The method of claim 11 , wherein each of the first, second and third sub-layers has a thickness within the range of about 200 Å to about 250 Å.

14. The method of claim 11 , wherein each of the curing steps used to cure the first, second and third sub-layers involves exposure to UV radiation for less than about 10 minutes.

15. The method of claim 11 , wherein each of the curing steps used to cure the first, second and third sub-layers involves exposure of the sub-layer to UV radiation for a duration of time within the range of about 5 to about 10 minutes.

16. The method of claim 1 , further comprising:

exposing each of the first cured sub-layer and the second cured sub-layer to a further curing step.

17. The method of claim 1 , wherein the semiconductor device is a CMOS device, wherein the first and second sub-layers are disposed over the NMOS region of the CMOS device, and wherein the first and second sub-layers are not disposed over the PMOS region of the CMOS device.

18. The method of claim 1 , wherein the semiconductor device comprises a silicide layer, and wherein the first and second sub-layers are disposed over the silicide layer.

19. The method of claim 1 , wherein the first and second sub-layers of stressor material form a stressor film, and wherein the stressor film has a tensile stress of at least about 1.2 GPa.

20. The method of claim 1 , wherein the first and second sub-layers of stressor material form a stressor film, and wherein the stressor film has a tensile stress of at least about 1.4 GPa.

21. The method of claim 1 , wherein the first and second sub-layers of stressor material form a stressor film, and wherein the stressor film has a tensile stress of at least about 1.5 GPa.

22. A method for making a semiconductor device, comprising:

providing a semiconductor structure equipped with first and second gate structures and channel regions, said channel regions being associated with the gate structures;

depositing a first sub-layer of a stressor material over the semiconductor structure, said stressor material containing silicon-nitrogen bonds and imparting tensile stress to the semiconductor structure;

curing the first stressor material through exposure to a UV radiation source;

depositing a second sub-layer of the stressor material over the first sub-layer;

curing the second sub-layer of stressor material through exposure to a UV radiation source;

depositing a third sub-layer of a third stressor material between the first and second gate structures and in contact with the second sub-layer;

curing the third stressor material through exposure to a radiation source;

depositing a fourth sub-layer of a fourth stressor material between the first and second gate structures and in contact with the third sub-layer; and

curing the fourth stressor material through exposure to radiation source.

Assignments (26)