IP Library Granted Patent US 7,554,391
Granted Patent B1
US 7,554,391 · App. 12/013,070 · Granted Jun 30, 2009

Amplifier having a virtual ground and method thereof

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Quick Facts
Patent No.
US 7,554,391
App. No.
12/013,070
Granted
Jun 30, 2009
Kind
B1
Abstract

An amplifier comprises first, second, and third modulators. The first modulator includes an input for receiving a first input signal, and an output for providing a first modulated output signal corresponding to the first input signal. The second modulator includes an input for receiving a second input signal, and an output for providing a second modulated output signal corresponding to the second input signal. The third modulator has an input for receiving a third input signal, and an output for providing a third modulated output signal corresponding to the third input signal and for providing a virtual ground. A first amplifier circuit is coupled to the outputs of the first and third modulators for driving a first load. A second amplifier circuit is coupled to the outputs of the second and third modulators for driving a second load.

Claims (55)

1. An amplifier comprising:

a first modulation circuit having an input for receiving a first input signal, and an output for providing a first modulated output signal, the first modulated output signal corresponding to the first input signal;

a second modulation circuit having an input for receiving a second input signal, and an output for providing a second modulated output signal, the second modulated output signal corresponding to the second input signal;

a third modulation circuit having an input for receiving a third input signal, and an output for providing a third modulated output signal, the third modulated output signal corresponding to the third input signal and for providing a virtual ground;

a first amplifier circuit coupled to the outputs of the first and third modulation circuits, the first amplifier circuit for driving a first load; and

a second amplifier circuit coupled to the outputs of the second and third modulation circuits, the second amplifier circuit for driving a second load.

2. The amplifier of claim 1 , wherein the first amplifier circuit comprises a first H-bridge circuit and the second amplifier circuit comprises a second H-bridge circuit.

3. The amplifier of claim 1 , wherein the third input signal represents a common mode voltage.

4. The amplifier of claim 1 , wherein the first, second, and third modulation circuits are characterized as being sigma delta modulation circuits.

5. The amplifier of claim 4 , wherein each of the sigma delta modulation circuits comprises:

a first summer having a first input for receiving the first input signal, a second input for receiving a feedback signal, and an output;

a delay element having an input coupled to the output of the first summer, and an output for providing the feedback signal;

a gain stage having an input coupled to the output of the delay element, and an output;

a second summer having a first input coupled to the output of the gain stage, a second input for receiving a feed-forward signal from the output of the first summer, and an output; and

a quantizer having an input coupled to the output of the second summer, and an output.

6. The amplifier of claim 5 , wherein each of the sigma delta modulation circuits further comprises a scale factor generator having a first input coupled to the output of the quantizer, a second input coupled to receive a power supply voltage, and an output coupled to a third input of the first summer, wherein the scale factor generator adds a scale factor to the first summer to compensate for variations of the power supply voltage.

7. The amplifier of claim 1 , wherein the amplifier is characterized as being a class D amplifier and the first, second, and third input signals are digital signals.

8. The amplifier of claim 1 , wherein the first, second, and third modulated output signals are characterized as being pulse density modulated output signals.

9. The amplifier of claim 1 , wherein the first amplifier circuit comprises a pair of series-connected transistors coupled between a power supply terminal and a ground terminal, the pair of series-connected transistors coupled to receive the first modulated output signal, and in response, to provide an amplified modulated output signal.

10. The amplifier of claim 1 , wherein the first amplifier circuit comprises a first H-bridge circuit and the second amplifier circuit comprises a second H-bridge circuit, wherein:

the first H-bridge circuit has a first input coupled to the output of the first modulation circuit and a second input coupled to the output of the third modulation circuit, the first H-bridge circuit having an output for driving the first load; and

the second H-bridge circuit has a first input coupled to the output of the second modulation circuit and a second input coupled to the output of the third modulation circuit, the second H-bridge circuit having an output for driving the second load.

11. An amplifier comprising:

a first sigma delta modulator having an input for receiving a first input signal, and an output for providing a first pulse density modulated output signal, the first pulse density modulated output signal corresponding to the first input signal;

a second sigma delta modulator having an input for receiving a second input signal, and an output for providing a second pulse density modulated output signal, the second pulse density modulated output signal corresponding to the second input signal;

a third sigma delta modulator having an input for receiving a third input signal, and an output for providing a third pulse density modulated output signal, the third pulse density modulated output signal corresponding to the third input signal and for providing a virtual ground;

a first H-bridge circuit coupled to the outputs of the first and third sigma delta modulators, the first H-bridge circuit for driving a first load; and

a second H-bridge circuit coupled to the outputs of the second and third sigma delta modulators, the second H-bridge circuit for driving a second load.

12. The amplifier of claim 11 , wherein the third input signal represents a common mode voltage of the first and second input signals.

13. The amplifier of claim 11 , wherein the first and second input signals are digital audio signals and each of the first and second loads is a speaker.

14. The amplifier of claim 11 , wherein the each of the first, second, and third sigma delta modulators comprises:

a first summer having a first input for receiving the first input signal, a second input for receiving a feedback signal, and an output;

a delay element having an input coupled to the output of the first summer, and an output for providing the feedback signal;

a gain stage having an input coupled to the output of the delay element, and an output;

a second summer having a first input coupled to the output of the gain stage, a second input for receiving a feed-forward signal from the output of the first summer, and an output; and

a quantizer having an input coupled to the output of the second summer, and an output.

15. The amplifier of claim 14 , wherein each of the first, second, and third sigma delta modulators further comprises a scale factor generator having a first input coupled to the output of the quantizer, a second input coupled to receive a power supply voltage, and an output coupled to a third input of the first summer, wherein the scale factor generator adds a scale factor to the first summer to compensate for variations of the power supply voltage.

16. A method for amplifying first and second stereo audio signals, the method comprising:

modulating the first stereo audio signal to provide a first modulated stereo signal;

modulating the second stereo audio signal to provide a second modulated stereo signal;

modulating a third signal to provide a third modulated signal, the third modulated signal for providing a virtual ground;

amplifying the first modulated stereo signal to drive a first load, wherein the first load is coupled to receive the first modulated stereo signal and the virtual ground; and

amplifying the second modulated stereo signal to drive a second load, wherein the second load is coupled to receive the second modulated stereo signal and the virtual ground.

17. The method of claim 16 , wherein modulating the first stereo audio signal, modulating the second stereo audio signal, and modulating the third signal each further comprise pulse density modulating each of the first stereo audio signal, the second stereo audio signal, and the third signal.

18. The method of claim 16 , wherein modulating the third signal further comprises providing a third signal that represents a common mode between the first and second stereo audio signals.

19. The method of claim 16 , wherein modulating the first stereo audio signal further comprises:

using a first summer, summing the first stereo audio signal input with a feedback signal to produce a summation signal;

delaying the first summation signal to generate a delayed summation signal;

feeding back the delayed summation signal to the first summer;

amplifying the delayed summation signal;

using a second summer, summing the delayed summation signal with a feed-forward signal from the first summer to produce a second summation signal; and

quantizing the second summation signal to produce a quantized signal.

20. The method of claim 19 , further comprising:

coupling the quantized signal to an input of a scale factor generator; and

feeding back an output of the scale factor generator to the first summer, wherein the scale factor generator adds a scale factor to the first summer to compensate for variations of the power supply voltage.

Assignments (20)
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 11759915 AND REPLACE IT WITH APPLICATION 11759935 PREVIOUSLY RECORDED ON REEL 040925 FRAME 0001. ASSIGNOR(S) HEREBY CONFIRMS THE RELEASE OF SECURITY INTEREST. Recorded Feb 17, 2020
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP, B.V. F/K/A FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 052917/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 11759915 AND REPLACE IT WITH APPLICATION 11759935 PREVIOUSLY RECORDED ON REEL 040928 FRAME 0001. ASSIGNOR(S) HEREBY CONFIRMS THE RELEASE OF SECURITY INTEREST. Recorded Jan 17, 2020
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP B.V.
Reel/Frame 052915/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 11759915 AND REPLACE IT WITH APPLICATION 11759935 PREVIOUSLY RECORDED ON REEL 037486 FRAME 0517. ASSIGNOR(S) HEREBY CONFIRMS THE ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS. Recorded Dec 10, 2019
From: CITIBANK, N.A.
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From: MORGAN STANLEY SENIOR FUNDING, INC.
To: SHENZHEN XINGUODU TECHNOLOGY CO., LTD.
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CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE PATENTS 8108266 AND 8062324 AND REPLACE THEM WITH 6108266 AND 8060324 PREVIOUSLY RECORDED ON REEL 037518 FRAME 0292. ASSIGNOR(S) HEREBY CONFIRMS THE ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS. Recorded Feb 1, 2017
From: CITIBANK, N.A.
To: MORGAN STANLEY SENIOR FUNDING, INC.
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RELEASE OF SECURITY INTEREST Recorded Nov 7, 2016
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP B.V.
Reel/Frame 040928/0001 →
RELEASE OF SECURITY INTEREST Recorded Sep 21, 2016
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP, B.V., F/K/A FREESCALE SEMICONDUCTOR, INC.
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ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Feb 4, 2016
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To: FREESCALE SEMICONDUCTOR, INC.
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To: FREESCALE SEMICONDUCTOR, INC.
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PATENT RELEASE Recorded Dec 21, 2015
From: CITIBANK, N.A., AS COLLATERAL AGENT
To: FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 037356/0143 →
PATENT RELEASE Recorded Dec 21, 2015
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To: FREESCALE SEMICONDUCTOR, INC.
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SECURITY AGREEMENT Recorded Nov 6, 2013
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To: CITIBANK, N.A., AS NOTES COLLATERAL AGENT
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SECURITY AGREEMENT Recorded Jun 18, 2013
From: FREESCALE SEMICONDUCTOR, INC.
To: CITIBANK, N.A., AS NOTES COLLATERAL AGENT
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SECURITY AGREEMENT Recorded May 13, 2010
From: FREESCALE SEMICONDUCTOR, INC.
To: CITIBANK, N.A., AS COLLATERAL AGENT
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From: ZUISS, THOMAS J.; TRAYLOR, KEVIN B.
To: FREESCALE SEMICONDUCTOR, INC.
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