System and a method for providing an output clock signal
View Patent ↗A system for providing an output clock signal, the system includes: (a) a first clock divider, adapted to receive an input clock signal and to provide a first divider output clock signal having a frequency that is lower than a frequency of the input clock signal; and (b) a second clock divider, adapted to select a second divider input clock signal out of the input clock signal and the first divider output clock signal, and to provide the output clock signal having a frequency that is lower than the frequency of the second divider input clock signal.
1. A system for providing an output clock signal, the system comprises:
a first clock divider, adapted to receive an input clock signal and to frequency divide the input clock signal to provide a first divider output clock signal having a frequency that is lower than a frequency of the input clock signal;
a second clock divider, adapted to select a second divider input clock signal out of the input clock signal and the first divider output clock signal, and to frequency divide the second divider input clock signal to provide the output clock signal having a frequency that is lower than the frequency of the second divider input clock signal, wherein the second clock driver is further adapted to select the second divider input clock signal out of a group comprising the input clock signal and multiple clock signals of different frequencies which are provided by multiple clock dividers; and
a third clock divider, adapted to receive a third divider input clock signal and to frequency divide the third divider input clock signal to provide a third divider output signal having a frequency that is lower than the frequency of the third divider input clock signal, wherein the selecting of the second divider input clock signal comprises selecting the second divider input clock signal out of the input clock signal, the first divider output clock signal and the third divider output clock signal;
wherein multiple clock dividers out of the first, second and third clock dividers are prevented from concurrently selecting the input clock signal and frequency dividing the input clock signal.
2. The system according to claim 1 , wherein the second clock divider is further adapted to determine a second divider division factor in response to the selected second divider input clock signal.
3. The system according to claim 2 , wherein a ratio between the second divider division factor and a received division factor sent to the second clock divider equals a ratio between the frequency of the first divider output clock signal and the frequency of the input clock signal.
4. The system according to claim 1 , wherein the second clock divider is adapted to indicate to the first clock divider if a provision of the first divider output clock signal is required.
5. The system according to claim 1 , wherein the second clock divider is adapted to select the first divider output clock signal as the second divider input clock signal if a ratio between the frequency of the first divider output clock signal and a required output frequency of the output clock signal is a positive integer.
6. The system according to claim 1 , comprising at least three clock dividers, wherein the second clock divider is adapted to select the second divider input clock signal out of the input clock signal and out of output clock signals outputted by another clock divider out of the at least three clock dividers.
7. The system according to claim 1 , wherein the second clock divider is adapted to select the second divider input clock signal in response to a power consumption related parameter.
8. The system according to claim 1 , further adapted to optimize a determination of multiple division factors of multiple clock dividers.
9. A method for providing an output clock signal, the method comprises:
(a) receiving, by a first clock divider, an input clock signal;
(b) providing, by the first clock divider and by frequency division, a first divider output clock signal having a
frequency that is lower than a frequency of the input clock signal;
(c) selecting, by a second clock divider, a second divider input clock signal out of the input clock signal and the first divider output clock signal, wherein the selecting comprises selecting the second divider input clock signal out of a group comprising the input clock signal and multiple clock signals of different frequencies which are provided by multiple clock dividers;
(d) providing, by the second clock divider and by frequency division, the output clock signal having a frequency that is lower than the frequency of the second divider input clock signal;
(e) selecting, by a third clock divider, a third divider input clock signal out of the input clock signal and the first divider output clock signal;
(f) providing, by the third clock divider and by frequency division, a third divider output clock signal having a frequency that is lower than the frequency of the third divider input clock signal; wherein the selecting of the second divider input clock signal comprises selecting the second divider input clock signal out of the input clock signal, the first divider output clock signal and the third divider output clock signal;
wherein multiple clock dividers out of the first, second and third clock dividers are prevented from concurrently selecting the input clock signal and frequency dividing the input clock signal.
10. The method according to claim 9 , further comprising determining a second divider division factor in response to the selected second divider input clock signal.
11. The method according to claim 10 , wherein the determining of the second divider division factor comprises determining the second divider division factor so that a ratio between the second divider division factor and a received division factor sent to the second clock divider equals a ratio between the frequency of the first divider output clock signal and the frequency of the input clock signal.
12. The method according to claim 9 , further comprising indicating, by the second clock divider, to the first clock divider if a provision of the first divider output clock signal is required.
13. The method according to claim 9 , wherein the selecting comprises selecting the first divider output clock signal as the second divider input clock signal if a ratio between the frequency of the first divider output clock signal and a required output frequency of the output clock signal is a positive integer.
14. The method according to claim 9 , wherein the selecting of the second divider input clock signal is responsive to a power consumption related parameter.
15. The method according to claim 9 , further comprising optimizing a determination of multiple division factors of multiple clock dividers.