Slew rate control of a charge pump
View Patent ↗A charge pump system including a clock circuit and a charge pump circuit is provided. The clock circuit provides a first clock with a frequency based on a memory block select signal indicative of load capacitance of a charge node. The charge pump circuit receives the first clock and charges the charge node at a rate based on the frequency of the first clock and the load capacitance of the charge node. The memory block select signal indicates which of the memory blocks are coupled to the charge node and thus indicates the load capacitance of the charge node. The frequency of the first clock is adjusted based on the load capacitance of the selected block so that the slew rate of the charge node is about the same. Thus, the slew rate of the voltage ramp on the charge node is about the same regardless of the load capacitance.
1. A charge pump system, comprising:
a clock circuit which provides a first clock with a frequency based on a memory block select signal indicative of load capacitance of a charge node; and
a charge pump circuit having an input receiving said first clock and an output which charges said charge node at a rate based on said frequency of said first clock and said load capacitance of said charge node, wherein said charge pump circuit comprises:
enable logic having a first input receiving said first clock, a second input receiving an enable signal, and an output providing a pump clock;
a charge pump having an input receiving said pump clock and an output coupled to said charge node; and
a comparator circuit having an input coupled to said charge node and an output providing said enable signal.
2. The charge pump system of claim 1 , wherein said clock circuit comprises:
conversion logic which converts said memory block select signal to a frequency select signal; and
a frequency divider which converts an input clock to said first clock based on said frequency select signal.
3. The charge pump system of claim 2 , wherein said frequency divider comprises:
a plurality of series-coupled flip-flops having an input receiving said input clock and a plurality of outputs providing a plurality of divided clocks; and
select logic having a plurality of data inputs coupled to said plurality of outputs of said plurality of series-coupled flip-flops, a select input receiving said frequency select signal, and an output providing said first clock.
4. The charge pump system of claim 2 , wherein said conversion logic comprises a memory programmed with a plurality of frequency select signals.
5. The charge pump system of claim 1 , wherein said clock circuit determines said load capacitance of said charge node based on said memory block select signal.
6. The charge pump system of claim 1 , wherein said comparator circuit comprises:
a capacitive voltage divider coupled to said charge node and having a sense node; and
a comparator having an input coupled to said sense node and an output providing said enable signal.
7. An integrated circuit (IC), comprising:
a plurality of memory blocks, each having a corresponding one of a plurality of sizes;
a control circuit which provides a memory block select to selectively couple a charge node to selected ones of said plurality of memory blocks; and
a charge pump system, comprising:
clock logic which provides a first clock with a frequency based on said memory block select; and
a charge pump circuit which charges said charge node at a rate based on said frequency of said first clock, wherein said charge pump circuit comprises:
a charge pump having an input receiving a pump clock and an output coupled to said charge node;
a comparator circuit having an input coupled to said charge node and an output providing an enable signal; and
enable logic having inputs receiving said enable signal and said first clock and an output providing said pump clock.
8. The IC of claim 7 , wherein each of said plurality of memory blocks comprises a block of floating gate non-volatile memory cells.
9. The IC of claim 7 , wherein said clock logic comprises:
conversion logic which converts said memory block select to a frequency select; and
a frequency divider which divides a frequency of an input clock to provide a plurality of divided clock signals and which selects from among said plurality of divided clock signals based on said frequency select.
10. The IC of claim 9 , wherein said conversion logic comprises a memory programmed with a plurality of frequency select values.
11. The IC of claim 7 , wherein said clock logic determines a combined capacitance of said selected ones of said plurality of memory blocks coupled to said charge node.
12. The IC of claim 7 , wherein said comparator circuit comprises:
a capacitive voltage divider coupled to said charge node and having a sense node; and
a comparator having an input coupled to said sense node and an output providing said enable signal.
13. A method of controlling slew rate of a charge pump, comprising:
coupling a voltage node to selected ones of a plurality of memory blocks based on a memory block select;
providing a first clock at a frequency based on the memory block select;
comparing a voltage of the voltage node with a predetermined voltage to provide an enable signal indicative thereof;
providing the first clock as a pump clock while the enable signal is provided; and
pumping charge into the voltage node while the pump clock is provided.
14. The method of claim 13 , wherein said providing a first clock comprises:
converting the memory block select to a frequency select;
providing a plurality of second clocks with different frequencies based on an input clock; and
selecting, based on the frequency select, one of the plurality of second clocks as the first clock.
15. The method of claim 14 , wherein said providing a plurality of second clocks comprises dividing a frequency of the input clock.
16. The method of claim 13 , wherein said providing a first clock comprises determining load capacitance of the voltage node based on combined capacitance of the selected ones of a plurality of memory blocks.
17. The method of claim 13 , wherein said comparing a level of the voltage node with a predetermined level comprises:
sensing the voltage of the voltage node and providing a sense voltage; and
comparing the sense voltage with a reference level to provide the enable signal indicative thereof.