Granted Patent B1

US 7,535,391 · App. 11/969,982 · Granted May 19, 2009

Abstract

Claims (79)

1. A method comprising:

providing an analog-to-digital converter (ADC) comprising a multiplying digital-to-analog converter (MDAC) having a plurality of capacitor positions;

generating a first random number for a first conversion cycle;

configuring each capacitor of the plurality of capacitors in a corresponding capacitor position of the plurality of capacitor positions based on the first random number for the first conversion cycle; and

converting, for the first conversion cycle, a first voltage of an analog signal to a first digital value using the ADC.

2. The method of claim 1 , further comprising:

generating a second random number for a second conversion cycle;

configuring each capacitor of the plurality of capacitors in a corresponding capacitor position of the plurality of capacitor positions based on the second random number for the second conversion cycle; and

converting, for the second conversion cycle, a second voltage of the analog signal to a second digital value using the ADC.

3. The method of claim 1 , wherein generating the first random number comprises generating a pseudo-random number.

4. The method of claim 1 , wherein the ADC comprises a redundant signed digit (RSD) stage comprising the MDAC.

5. The method of claim 1 , wherein:

the MDAC comprises an amplifier, a first capacitor position, a second capacitor position, a third capacitor position, and a fourth capacitor position; and

converting the first voltage to the first digital value comprises:

during a first phase of the first conversion cycle:

coupling a capacitor configured in the first capacitor position to a first sample configuration, the first sample configuration comprising a first capacitor electrode coupled to the input analog signal and a second capacitor electrode coupled to a first voltage reference;

coupling a capacitor configured in the second capacitor position to the first sample configuration;

coupling a capacitor configured in the third capacitor position to the first sample configuration; and

coupling a capacitor configured in the fourth capacitor position to the first sample configuration.

6. The method of claim 5 , wherein converting the first voltage to the first digital value further comprises:

during a second phase of the first conversion cycle following the first phase:

coupling the capacitor configured in the first capacitor position to a first gain configuration, the first gain configuration comprising the first capacitor electrode coupled to a second voltage reference and the second capacitor electrode coupled to an input of the amplifier;

coupling the capacitor configured in the second capacitor position to the first gain configuration;

coupling the capacitor configured in the third capacitor position to the first gain configuration; and

coupling the capacitor configured in the fourth capacitor position to a second gain configuration, the second gain configuration comprising the first capacitor electrode coupled to an output of the amplifier and the second capacitor electrode coupled to the input of the amplifier.

7. The method of claim 6 , wherein converting the first voltage to the first digital value further comprises:

during a third phase of the first conversion cycle following the second phase:

coupling the capacitor configured in the third capacitor position to a second sample configuration, the second sample configuration comprising the first capacitor electrode coupled to the output of the amplifier and the second capacitor electrode coupled to the first voltage reference; and

coupling the capacitor configured in the fourth capacitor position to the second sample configuration; and

during a fourth phase of the first conversion cycle following the third phase:

coupling the capacitor configured in the third capacitor position to the first gain configuration;

coupling the capacitor configured in the fourth capacitor position to the second gain configuration;

coupling the capacitor configured in the first capacitor position to the second sample configuration; and

coupling the capacitor configured in the second capacitor position to the second sample configuration.

8. An analog-to-digital converter (ADC) comprising:

a random number generator to generate a random number; and

a multiplying digital-to-analog converter (MDAC) comprising:

an amplifier;

a plurality of capacitor positions, each selectively coupleable to the amplifier in a corresponding sequence of sample and gain configurations for a corresponding sequence of phases of a conversion cycle;

a plurality of capacitors; and

a first switch network configured to selectively configure each capacitor of the plurality of capacitors in a corresponding capacitor position of the plurality of capacitor positions based on the random number.

9. The ADC of claim 8 , further comprising:

a second switch network configured to selectively couple each capacitor coupled to a corresponding capacitor position in the corresponding sequence of sample and gain configurations during the conversion cycle.

10. The ADC of claim 9 , wherein:

the plurality of capacitor configurations comprises a first capacitor position, a second capacitor position, a third capacitor position, and a fourth capacitor position; and

the second switch network is configured to:

couple a capacitor configured in the first capacitor position to a first sample configuration during a first phase of the conversion cycle, the first sample configuration comprising a first capacitor electrode coupled to a select one of an output of the amplifier or a first voltage reference and a second capacitor electrode coupled to a first voltage reference;

couple a capacitor configured in the second capacitor position to the first sample configuration during the first phase;

couple a capacitor configured in the third capacitor position to the first sample configuration during the first phase; and

couple a capacitor configured in the fourth capacitor position to the first sample configuration during the first phase.

11. The ADC of claim 10 , wherein the second switch network further is configured to:

couple the capacitor configured in the first capacitor position to a first gain configuration during a second phase of the conversion cycle following the first phase, the first gain configuration comprising the first capacitor electrode coupled to a second voltage reference and the second capacitor electrode coupled to an input of the amplifier;

couple the capacitor configured in the second capacitor position to the first gain configuration during the second phase;

couple the capacitor configured in the third capacitor position to the first gain configuration during the second phase; and

couple the capacitor configured in the fourth capacitor position to a second gain configuration during the second phase, the second gain configuration comprising the first capacitor electrode coupled to an output of the amplifier and the second capacitor electrode coupled to the input of the amplifier.

12. The ADC of claim 8 , wherein:

the random number generator is configured to generate a random number for each conversion cycle of a plurality of conversion cycles; and

the first switch network is configured to selectively couple each capacitor of the plurality of capacitors to a corresponding capacitor position of the plurality of capacitor position for each conversion cycle of the plurality of conversion cycles based on the random number generated for the corresponding conversion cycle.

13. The ADC of claim 8 , further comprising a redundant signed digit (RSD) stage comprising the MDAC.

14. The ADC of claim 13 , further comprising:

an analog input terminal configured to receive an analog input signal;

the RSD stage configured to:

produce a first number of bits at a digital output from the analog input signal during a first phase of the conversion cycle;

provide a residual voltage of the analog input signal at the analog input terminal during a second phase of the conversion cycle; and

provide a second number of bits from the residual voltage during third phase of the conversion cycle, the second number of bits less than the first number of bits; and

a digital section configured to perform a digital alignment and correction on the first number of bits and the second number of bits to generate a digital value.

15. The ADC of claim 8 , wherein the random number generator comprises a pseudo-random number generator.

16. An analog-to-digital converter (ADC) comprising:

a multiplying digital-to-analog converter (MDAC) having a plurality of capacitor positions;

a random number generator configured to generate a first random number for a first conversion cycle;

means for coupling each capacitor of the plurality of capacitors in a corresponding capacitor position of the plurality of capacitor positions based on the first random number for the first conversion cycle; and

means for converting, for the first conversion cycle, a first voltage of an analog signal to a first digital value using the MDAC.

17. The ADC of claim 16 , wherein:

the random number generator is further configured to generate a second random number for a second conversion cycle;

the means for coupling comprises means for coupling each capacitor of the plurality of capacitors to a corresponding capacitor position of the plurality of capacitor positions based on the second random number for the second conversion cycle; and

the means for converting comprises means for converting, for the second conversion cycle, a second voltage of the analog signal to a second digital value using the ADC.

18. The ADC of claim 16 , wherein the random number generator comprises a pseudo-random number generator.

19. The ADC of claim 16 , wherein the ADC comprises a redundant signed digit (RSD) stage comprising the MDAC.

20. The ADC of claim 19 , wherein the RSD stage comprises a multiple-stage RSD.

Assignments (15)