Hardware managed context sensitive interrupt priority level control
View Patent ↗A flexible interrupt controller circuit and methodology are provided which use an interrupt circuit ( 300 ) that multiplexes ( 324 ) a plurality of interrupt priority registers ( 321, 322 ) based on the current context of the system that is identified in mode control selector ( 326 ). By using the mode control selector ( 326 ) to selectively couple different priority level assignments to a priority encoding module ( 330 ), context sensitive switching of the priority levels assigned to each interrupt request can be implemented with reduced latency. The context switch could be based on an OS context ID, power management modes, security modes, and other system defined modes where priority levels would differ. The selected priority level information is used to provide an interrupt request signal ( 332 ) which will cause an interrupt to occur in the data processing system.
1. A method for implementing interrupts in a data processing system, comprising:
receiving one or more interrupt requests from one or more interrupt sources;
selectively masking the one or more interrupt requests to generate one or more pending interrupt signals;
providing a plurality of interrupt priority storage devices comprising a first interrupt priority storage device for storing priority level information associated with a first system mode, and a second interrupt priority storage device for storing priority level information associated with a second system mode; and
providing a plurality of interrupt priority storage devices comprising a first interrupt priority storage device for storing priority level information associated with a first system mode for each of the one or more interrupt requests, and a second interrupt priority storage device for storing priority level information associated with a second system mode for each of the one or more interrupt requests; and
selectively coupling, in response to a mode control signal, one of the plurality of interrupt priority storage devices to provide logic circuitry with priority level information corresponding to the mode control signal, where the logic circuitry uses the provided priority level information to prioritize one or more of the pending interrupt signals and also provides an interrupt request signal which will cause an interrupt to occur in the data processing system.
2. The method of claim 1 , where providing the plurality of interrupt priority storage devices comprises providing a first interrupt priority storage device for storing priority level information associated with a low power system mode, and providing a second interrupt priority storage device for storing priority level information associated with a normal power system mode.
3. The method of claim 1 , where providing the plurality of interrupt priority storage devices comprises providing a first interrupt priority storage device for storing priority level information associated with a high security system mode, and providing a second interrupt priority storage device for storing priority level information associated with a low security system mode.
4. The method of claim 1 , where selectively coupling, in response to a mode control signal, one of the plurality of interrupt priority storage devices to provide logic circuitry with priority level information, comprises:
providing a multiplexer circuit having a plurality of inputs, where each of the plurality of inputs is coupled to receive priority level information from one of the plurality of interrupt priority storage devices, and
applying a mode control signal as a control input to the multiplexer circuit to select priority level information from one of the plurality of interrupt priority storage devices as an output to the multiplexer circuit that is provided to the logic circuitry.
5. The method of claim 1 , further comprising selectively coupling, in response to a second mode control signal, a second one of the plurality of interrupt priority storage devices to provide the logic circuitry with different priority level information corresponding to the second mode control signal, where the logic circuitry uses the different priority level information to prioritize one or more of the pending interrupt signals and provide an interrupt request signal which will cause an interrupt to occur in the data processing system.
6. The method of claim 1 , where the first interrupt priority storage device stores first priority level information associated with a first system mode, and the second interrupt priority storage device stores second priority level information associated with a second system mode that is different from the first priority level information.
7. The method of claim 1 , where providing the plurality of interrupt priority storage devices comprises storing one or more multi-bit priority level indications in each of the plurality of interrupt priority storage devices.
8. The method of claim 1 , where providing the plurality of interrupt priority storage devices comprises storing one or more multi-bit priority level indications in each of the plurality of interrupt priority storage devices, where each multi-bit priority level indication is assigned to a corresponding pending interrupt signal.
9. A data processing system, comprising:
at least a first interrupt source for generating a pending interrupt request;
a plurality of interrupt priority storage devices comprising a first interrupt priority storage device for storing priority level information associated with a first system mode, and a second interrupt priority storage device for storing priority level information associated with a second system mode;
a selection circuit coupled to the plurality of interrupt priority storage devices for outputting selected priority level information in response to a mode control signal; and
a priority encoder coupled to receive the pending interrupt request and the selected priority level information, where the priority encoder uses the selected priority level information to prioritize the pending interrupt request and also provides a prioritized interrupt request signal which will cause an interrupt to occur in the data processing system.
10. The data processing system of claim 9 , where the first interrupt source is located in a peripheral module which comprises the plurality of interrupt priority storage devices and the selection circuit.
11. The data processing system of claim 9 , where the at least a first interrupt source comprises a plurality of interrupt sources for generating a plurality of pending interrupt requests.
12. The data processing system of claim 11 , comprising a centralized interrupt control circuit which comprises the plurality of interrupt priority storage devices, the selection circuit and the priority encoder coupled to receive the plurality of pending interrupt requests and the selected priority level information, where the priority encoder uses the selected priority level information to prioritize the plurality of pending interrupt requests and provide a prioritized interrupt request signal which will cause an interrupt to occur in the data processing system.
13. The data processing system of claim 9 , further comprising a masking logic device coupled to receive an interrupt request from the first interrupt source and also coupled to receive one or more masking bits from an enable register, where the masking logic device generates the pending interrupt request by selectively masking the interrupt request with the one or more masking bits.
14. The data processing system of claim 9 , wherein the plurality of interrupt priority storage devices are each implemented as latch circuits.
15. The data processing system of claim 9 , where the plurality of interrupt priority storage devices comprises a first interrupt priority storage device for storing priority level information associated with a low power system mode, and a second interrupt priority storage device for storing priority level information associated with a normal power system mode.
16. The data processing system of claim 9 , where the plurality of interrupt priority storage devices comprises a first interrupt priority storage device for storing priority level information associated with a high security system mode, and a second interrupt priority storage device for storing priority level information associated with a low security system mode.
17. A method for implementing interrupts in a data processing system, comprising:
generating one or more pending interrupt requests from one or more interrupt sources, each pending interrupt request indicating an interrupt request from a different interrupt source;
storing a plurality of sets of priority levels in one or more storage devices, where each set of priority levels is associated with a different system mode and specifies a priority level for each potential pending interrupt request;
coupling a priority encoder circuit to the one or more storage devices to receive a first set of priority levels from the plurality of sets of priority levels in response to a mode control signal, where the priority encoder circuit uses the first set of priority levels to prioritize the one or more of the pending interrupt requests; and
generating at the priority encoder circuit an interrupt request signal which will cause an interrupt to occur in the data processing system, thereby dynamically changing prioritization of servicing of the pending interrupt requests in the data processing system.
18. The method of claim 17 , where generating one or more pending interrupt requests comprises masking the one or more interrupt requests to selectively pass pending interrupt requests to the priority encoder circuit in response to an enable signal.
19. The method of claim 17 , where coupling the priority encoder circuit to the one or more storage devices comprises:
providing a selection circuit having a plurality of inputs, where each of the plurality of inputs is coupled to receive a set of priority levels from the one or more storage devices, and
applying a mode control signal as a control input to the selection circuit to select a set of priority levels from one or more storage devices as an output to the selection circuit that is provided to the priority encoder.
20. The method of claim 17 , where storing a plurality of sets of priority levels in one or more storage devices comprises storing one or more multi-bit priority level indications that are associated with a first system mode in a first storage device, where each multi-bit priority level indication is assigned to a corresponding potential pending interrupt request.