Nonvolatile memory cell programming
View Patent ↗A method for programming a non-volatile memory (NVM) cell includes applying an increasing voltage to the current electrode that is used as a source during a read. The initial programming source voltage results in a relatively small number of electrons being injected into the storage layer. Because of the relatively low initial voltage level, the vertical field across the gate dielectric is reduced. The subsequent elevation of the source voltage does not raise the vertical field significantly due to the electrons in the storage layer establishing a field that reduces the vertical field. With less damage to the gate dielectric during programming, the endurance of the NVM cell is improved.
1. A method of programming a non-volatile memory (NVM) cell that includes a first current electrode that functions as a source during a read operation, a second current electrode that functions as a drain during a read operation, and a control electrode that functions as a biasing gate, the method comprising:
applying a first programming voltage to the first current electrode;
applying a second programming voltage to the first current electrode after the applying the first programming voltage, wherein the second programming voltage is greater than the first programming voltage; and
applying a programming voltage to the control electrode during the step of applying the first programming voltage and applying a programming voltage to the control electrode during the step of applying the second programming voltage.
2. The method of claim 1 , wherein the applying the first programming voltage is characterized as being performed by ramping up to the first programming voltage.
3. The method of claim 2 , wherein the applying the second programming voltage is further characterized as being performed by ramping from the first programming voltage to the second programming voltage.
4. The method of claim 1 , wherein:
the first programming voltage is applied for a first time duration; and
the second programming voltage is applied for a second time duration.
5. The method of claim 4 wherein the second time duration is longer than the first time duration.
6. The method of claim 1 , wherein the NVM cell is selected during the applying a programming voltage to the control electrode, wherein the NVM cell is deselected between the applying the first programming voltage and the applying the second programming voltage.
7. The method of claim 1 , wherein the first programming voltage and the second programming voltage are greater than a voltage applied to the control electrode during the step of applying a first programming voltage to the first current electrode and the step of applying a second programming voltage to the first current electrode.
8. The method of claim 1 wherein:
the second current electrode is at a third voltage before the step of applying a first programming voltage to the first current electrode;
the second current electrode is at a voltage different than the third voltage during the step applying a first programming voltage to the first current electrode;
the second current electrode is at a voltage different than the third voltage during the step applying a second programming voltage to the first current electrode.
9. The method of claim 1 , wherein the applying the second programming voltage uninterruptibly follows from the applying the first programming voltage.
10. The method of claim 1 , further comprising applying a third programming voltage to the first current electrode after the applying the first programming voltage, wherein the third programming voltage is greater than the second programming voltage.
11. The method of claim 10 , wherein the applying the third programming voltage is further characterized as being performed by ramping from the second programming voltage to the third programming voltage.
12. The method of claim 10 , wherein the applying the third programming voltage uninterruptibly follows from the applying the second programming voltage.
13. The method of claim 10 , wherein:
the first programming voltage is applied for a first time duration;
the second programming voltage is applied for a second time duration;
the third programming voltage is applied for a third time duration.
14. The method of claim 13 wherein the third time duration is longer than the first time duration and the third time duration is longer than the second time duration.
15. The method of claim 10 , further comprising:
deselecting the NVM cell between the applying the second programming voltage and the applying the third programming voltage.
16. The method of claim 1 , wherein the NVM cell has a storage layer selected from the group consisting of a metal layer, a polysilicon layer, a layer of nanocrystals, and a charge storing dielectric layer.
17. The method of claim 1 wherein the applying a first programming voltage to the first current electrode and the applying a second programming voltage to the first current electrode is further characterized as being performed by ramping through the first programming voltage to the second programming voltage.
18. A method of programming a non-volatile memory (NVM) cell that includes a biasing gate, a source, and a drain for reading the NVM cell, the method comprising:
applying a first voltage to the source for a first time duration;
after the applying the first voltage and before performing a read of the NVM cell, applying a second voltage to the source for a second time duration, wherein the second voltage is greater than the first voltage; and
after applying the second voltage and before performing a read of the NVM cells, applying a third voltage to the source for a third time duration, wherein the third voltage is greater than the second voltage.
19. The method of claim 18 wherein the third time duration is longer than the first time duration and the third time duration is longer than the second time duration.
20. A method for programming an NVM cell including a biasing gate, a source, and a drain for reading, the method including an uninterruptible portion comprising:
applying a first voltage to the source;
applying a second voltage to the source, wherein the second voltage is greater than the first voltage;
applying a third voltage to the source, wherein the third voltage is greater than the second voltage; and
applying a voltage to the biasing gate during the applying the first voltage to the source, applying a voltage to the biasing gate during the applying the second voltage to the source, and applying a voltage to the biasing gate during the applying the third voltage to the source.