IP Library Granted Patent US 7,320,931
Granted Patent B2
US 7,320,931 · App. 10/903,841 · Granted Jan 22, 2008

Interfacial layer for use with high k dielectric materials

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Quick Facts
Patent No.
US 7,320,931
App. No.
10/903,841
Granted
Jan 22, 2008
Kind
B2
Abstract

Methods and apparatus are provided for depositing a layer of pure germanium can on a silicon substrate. This germanium layer is very thin, on the order of about 14 Å, and is less than the critical thickness for pure germanium on silicon. The germanium layer serves as an intermediate layer between the silicon substrate and the high k gate layer, which is deposited on the germanium layer. The germanium layer helps to avoid the development of an oxide interfacial layer during the application of the high k material. Application of the germanium intermediate layer in a semiconductor structure results in a high k gate functionality without the drawbacks of series capacitance due to oxide impurities. The germanium layer further improves mobility.

Claims (30)

1. A method for forming a semiconductor structure comprising the steps of:

providing a silicon substrate with an exposed surface;

inhibiting formation of one or more oxides on the exposed surface of the silicon substrate, wherein inhibiting comprises the steps of:

cleaning the exposed surface of the silicon substrate to reduce the presence of oxides;

depositing a layer of substantially pure germanium directly on the cleaned, exposed surface of the silicon substrate such that the germanium layer is less than approximately 14 Å in thickness and is epitaxially matched to the silicon substrate, wherein the deposited substantially pure germanium layer has an exposed surface; and

cleaning the exposed surface of the substantially pure germanium layer to reduce the presence of oxides; and

forming a dielectric layer of high k material directly on the cleaned, exposed surface of the substantially pure germanium layer.

2. The method according to claim 1 wherein the step of providing the substrate layer further comprises providing a silicon layer with an exposed surface of single crystal silicon.

3. The method according to claim 1 wherein the step of providing the substrate layer further comprises providing a gallium arsenide layer with an exposed surface of single crystal gallium arsenide or its alloy compounds.

4. The method according to claim 1 wherein the step of providing the substrate layer further comprises providing an indium phosphide layer with an exposed surface of single crystal indium phosphide or its alloy compounds.

5. The method according to claim 1 wherein the step of depositing the layer of substantially pure germanium comprises depositing a layer of substantially pure germanium through a chemical vapor deposition (CVD) process.

6. The method according to claim 1 wherein the step of depositing the layer of substantially pure germanium comprises depositing a layer of substantially pure germanium through a molecular beam epitaxy (MBE) process.

7. The method according to claim 1 wherein the step of depositing the layer of substantially pure germanium comprises depositing a layer of substantially pure germanium through an atomic layer deposition (ALD) process.

8. The method according to claim 1 wherein the step of depositing the substantially pure germanium layer further comprises growing a substantially pure germanium layer in the 2-dimensional growth mode.

9. The method according to claim 1 wherein the step of depositing the substantially pure germanium layer further comprises depositing a substantially pure germanium layer having three or less atomic layers in the germanium crystal lattice.

10. The method according to claim 1 wherein the step of depositing one of the dielectric layer and the stack of dielectric layers of high k material further comprises utilizing a dielectric material selected from a group consisting of hafnium oxides, zirconium oxides, titanium oxides, aluminum oxides, silicates, and hafnium nitrides.

11. A method for forming a semiconductor structure comprising the steps of:

providing a high purity single crystal silicon substrate layer with an exposed surface;

inhibiting formation of one or more oxides on the exposed surface of the substrate, wherein inhibiting comprises the steps of:

cleaning the exposed surface of the substrate layer to reduce the presence of oxides;

depositing a layer of high purity germanium on the cleaned, exposed surface of the substrate layer wherein the germanium layer is epitaxially matched to the substrate layer and includes up to 5% carbon and such that the germanium layer is less than a critical thickness, and wherein the deposited germanium layer has an exposed surface; and

cleaning the exposed surface of the germanium layer to reduce the presence of oxides; and

depositing a dielectric layer of high k material on the cleaned, exposed surface of the germanium layer.

12. The method according to claim 11 wherein the step of depositing the layer of high purity germanium further comprises depositing a high purity layer of germanium such that the germanium layer is less than approximately 14 Å in thickness.

13. The method according to claim 11 wherein the step of depositing the dielectric layer further comprises depositing a dielectric layer that is less than approximately 100 Å in thickness.

14. The method according to claim 11 wherein the step of depositing the dielectric layer of high k material further comprises a dielectric material selected from a group consisting of hafnium oxides, zirconium oxides, titanium oxides, aluminum oxides, silicates, hafnium nitrides, germanium oxynitrides, and lanthanum oxides.

15. The method according to claim 11 wherein the step of depositing the dielectric layer further comprises depositing a dielectric layer that is between approximately 60 to approximately 80 Å in thickness.

16. The method according to claim 11 wherein the step of depositing the layer of germanium comprises depositing a layer of germanium through a chemical vapor deposition (CVD) deposition process.

17. The method according to claim 11 wherein the step of depositing the layer of germanium comprises depositing a layer of germanium through a molecular beam epitaxy (MBE) process.

18. The method according to claim 11 wherein the step of depositing the layer of germanium comprises depositing a layer of germanium through an atomic layer deposition (ALD) process.

Assignments (23)
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 11759915 AND REPLACE IT WITH APPLICATION 11759935 PREVIOUSLY RECORDED ON REEL 040925 FRAME 0001. ASSIGNOR(S) HEREBY CONFIRMS THE RELEASE OF SECURITY INTEREST. Recorded Feb 17, 2020
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP, B.V. F/K/A FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 052917/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 11759915 AND REPLACE IT WITH APPLICATION 11759935 PREVIOUSLY RECORDED ON REEL 040928 FRAME 0001. ASSIGNOR(S) HEREBY CONFIRMS THE RELEASE OF SECURITY INTEREST. Recorded Jan 17, 2020
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP B.V.
Reel/Frame 052915/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 11759915 AND REPLACE IT WITH APPLICATION 11759935 PREVIOUSLY RECORDED ON REEL 037486 FRAME 0517. ASSIGNOR(S) HEREBY CONFIRMS THE ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS. Recorded Dec 10, 2019
From: CITIBANK, N.A.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 053547/0421 →
RELEASE OF SECURITY INTEREST Recorded Sep 10, 2019
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP B.V.
Reel/Frame 050744/0097 →
CORRECTIVE ASSIGNMENT TO CORRECT THE TO CORRECT THE APPLICATION NO. FROM 13,883,290 TO 13,833,290 PREVIOUSLY RECORDED ON REEL 041703 FRAME 0536. ASSIGNOR(S) HEREBY CONFIRMS THE THE ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS.. Recorded Feb 20, 2019
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: SHENZHEN XINGUODU TECHNOLOGY CO., LTD.
Reel/Frame 048734/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE PATENTS 8108266 AND 8062324 AND REPLACE THEM WITH 6108266 AND 8060324 PREVIOUSLY RECORDED ON REEL 037518 FRAME 0292. ASSIGNOR(S) HEREBY CONFIRMS THE ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS. Recorded Feb 1, 2017
From: CITIBANK, N.A.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 041703/0536 →
CORRECTIVE ASSIGNMENT TO CORRECT THE NATURE OF CONVEYANCE LISTED CHANGE OF NAME SHOULD BE MERGER AND CHANGE PREVIOUSLY RECORDED AT REEL: 040652 FRAME: 0180. ASSIGNOR(S) HEREBY CONFIRMS THE MERGER AND CHANGE OF NAME. Recorded Jan 12, 2017
From: FREESCALE SEMICONDUCTOR INC.
To: NXP USA, INC.
Reel/Frame 041354/0148 →
CHANGE OF NAME Recorded Nov 8, 2016
From: FREESCALE SEMICONDUCTOR INC.
To: NXP USA, INC.
Reel/Frame 040652/0180 →
RELEASE OF SECURITY INTEREST Recorded Nov 7, 2016
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP B.V.
Reel/Frame 040928/0001 →
RELEASE OF SECURITY INTEREST Recorded Sep 21, 2016
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP, B.V., F/K/A FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 040925/0001 →
SUPPLEMENT TO THE SECURITY AGREEMENT Recorded Jun 16, 2016
From: FREESCALE SEMICONDUCTOR, INC.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 039138/0001 →
ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS Recorded Jan 13, 2016
From: CITIBANK, N.A.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 037518/0292 →
ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS Recorded Jan 12, 2016
From: CITIBANK, N.A.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 037486/0517 →
PATENT RELEASE Recorded Dec 21, 2015
From: CITIBANK, N.A., AS COLLATERAL AGENT
To: FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 037354/0225 →
PATENT RELEASE Recorded Dec 21, 2015
From: CITIBANK, N.A., AS COLLATERAL AGENT
To: FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 037356/0553 →
PATENT RELEASE Recorded Dec 21, 2015
From: CITIBANK, N.A., AS COLLATERAL AGENT
To: FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 037356/0143 →
PATENT RELEASE Recorded Dec 21, 2015
From: CITIBANK, N.A., AS COLLATERAL AGENT
To: FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 037354/0688 →
SECURITY AGREEMENT Recorded Nov 6, 2013
From: FREESCALE SEMICONDUCTOR, INC.
To: CITIBANK, N.A., AS NOTES COLLATERAL AGENT
Reel/Frame 031591/0266 →
SECURITY AGREEMENT Recorded Jun 18, 2013
From: FREESCALE SEMICONDUCTOR, INC.
To: CITIBANK, N.A., AS NOTES COLLATERAL AGENT
Reel/Frame 030633/0424 →
SECURITY AGREEMENT Recorded May 13, 2010
From: FREESCALE SEMICONDUCTOR, INC.
To: CITIBANK, N.A., AS COLLATERAL AGENT
Reel/Frame 024397/0001 →
SECURITY AGREEMENT Recorded Jul 7, 2008
From: FREESCALE SEMICONDUCTOR, INC.
To: CITIBANK, N.A.
Reel/Frame 021194/0593 →
SECURITY AGREEMENT Recorded Feb 2, 2007
From: FREESCALE SEMICONDUCTOR, INC.; FREESCALE ACQUISITION CORPORATION; FREESCALE ACQUISITION HOLDINGS CORP.; FREESCALE HOLDINGS (BERMUDA) III, LTD.
To: CITIBANK, N.A. AS COLLATERAL AGENT
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ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jul 30, 2004
From: THOMAS, SHAWN G.; MANIAR, PAPU D.; ILDEREM, VIDA
To: FREESCALE SEMICONDUCTOR INC.
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