IP Library Granted Patent US 8,168,468
Granted Patent B2
US 8,168,468 · App. 12/039,909 · Granted May 1, 2012

Method of making a semiconductor device including a bridgeable material

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Quick Facts
Patent No.
US 8,168,468
App. No.
12/039,909
Granted
May 1, 2012
Kind
B2
Abstract

A method for making a semiconductor device ( 10 ) includes providing an interconnect layer ( 14 ) over an underlying layer ( 12 ), forming a first insulating layer ( 16 ) over the interconnect layer, and forming an opening ( 18 ) through the insulating layer to the interconnect layer. A first conductive layer ( 24 ) is formed over the interconnect layer and in the opening. This is performed by plating so it is selective. A second conductive layer ( 28 ) in the opening is formed by displacement by immersion. This is performed after the first conductive layer has been formed. The result is the second conductive layer is formed by a selective deposition and is effective for providing it with bridging material. A layer of bridgeable material ( 34 ) is formed over the second conductive layer and in the opening. A third conductive layer ( 42 ) is formed over the bridgeable material. The semiconductor device may be useable as a conductive bridge memory device.

Claims (51)

1. A method for making a semiconductor device, comprising:

providing an interconnect layer over an underlying layer;

forming a first insulating layer over the interconnect layer;

forming an opening through the insulating layer to the interconnect layer;

forming a first conductive layer over the interconnect layer and in the opening by plating;

forming a second conductive layer in the opening by immersion, wherein:

the second conductive layer is formed after the first conductive layer;

during immersion, the second conductive layer displaces a portion of the first conductive layer; and

the second conductive layer comprises bridging material;

forming a barrier layer over the second conductive layer;

forming a layer of bridgeable material over the barrier layer; and

forming a third conductive layer over the bridgeable material.

2. The method of claim 1 further comprising applying energy to the second conductive layer for forming clusters of bridging material in the layer of bridgeable material, wherein the clusters comprise bridging material from the second conductive layer.

3. The method of claim 1 further comprising applying a voltage between the interconnect layer and the third conductive layer to form a bridge of bridging material between the second conductive layer and the third conductive layer, wherein the clusters are connected by bridging material.

4. The method of claim 2 , wherein the step of forming the second conductive layer causes a replacement of a top portion of the first conductive layer.

5. The method of claim 4 , wherein the step of forming the second conductive layer is further characterized by bridging material comprising silver.

6. The method of claim 5 , wherein the step of forming the first conductive layer is further characterized by the first conductive layer comprising copper.

7. The method of claim 5 , wherein the step of forming the bridgeable material is further characterized by the bridgeable material comprising a chalcogenide.

8. The method of claim 5 , wherein the step of forming the bridgeable material is further characterized by the bridgeable material comprising an oxide.

9. The method of claim 1 , further comprising:

forming a second insulating layer over the first insulating layer and in the opening, wherein the second insulating layer is conformal, wherein the forming the second insulating layer is performed before forming the first conductive layer and the second insulating layer is of a different type of material from the first insulating layer; and

anisotropically etching the second insulating layer to result in a sidewall spacer along a sidewall of the opening.

10. The method of claim 1 , further comprising forming another barrier along a sidewall of the opening before forming the first conductive layer.

11. The method of claim 1 , wherein the barrier layer comprises one of a group consisting of cobalt and nickel, one of a group consisting of tungsten, molybdenum, and rhenium, and one of a group consisting of boron and phosphorus.

12. A method of forming a semiconductor device, comprising:

providing an interconnect layer over an underlying layer;

forming a first insulating layer over the interconnect layer;

forming an opening through the insulating layer to the interconnect layer;

forming a first conductive layer over the interconnect layer and in the opening by selective deposition, wherein the first conductive layer comprises bridging material;

forming a barrier layer over the first conductive layer;

forming a layer of bridgeable material over barrier layer; and

forming a second conductive layer over the bridgeable material.

13. The method of claim 12 , wherein the step of forming the first conductive layer is further characterized by the first conductive layer comprising copper.

14. The method of claim 12 , wherein the step of forming the layer of bridgeable material is further characterized by the layer of bridgeable material being a chalcogenide.

15. The method of claim 12 , wherein the step of forming the layer of bridgeable material is further characterized by the layer of bridgeable material being an oxide.

16. The method of claim 12 , further comprising:

forming a second insulating layer over the first insulating layer and in the opening, wherein the second insulating layer is conformal, wherein the forming the second insulating layer is performed before forming the first conductive layer and the second insulating layer is of a different type of material from the first insulating layer; and

anisotropically etching the second insulating layer to result in a sidewall spacer along a sidewall of the opening.

17. The method of claim 12 wherein the barrier layer comprises one of a group consisting of cobalt and nickel, one of a group consisting of tungsten, molybdenum, and rhenium, and one of a group consisting of boron and phosphorus.

18. A semiconductor memory device, comprising:

an interconnect layer over an underlying layer;

a first insulating layer over the interconnect layer;

an opening in the insulating layer to the interconnect layer;

a first conductive layer over the interconnect layer and in the opening, wherein the first conductive layer comprises a bridging material;

a first barrier over the first conductive layer;

a layer of bridgeable material over the first barrier; and

a second conductive layer over the bridgeable material.

19. The semiconductor memory device of claim 18 , further comprising a second barrier along a sidewall of the opening, wherein the second barrier is characterized as being an insulator and functions as a diffusion barrier between the first insulating layer and the first conductive layer.

20. The semiconductor memory device of claim 19 , wherein:

the second barrier allows transfer of material between the first conductive layer and the layer of bridgeable material during programming and erasing of the semiconductor memory device; and

the second barrier blocks transfer of material between the first conductive layer and the layer of bridgeable material during reading of the semiconductor memory device.

Assignments (17)
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 11759915 AND REPLACE IT WITH APPLICATION 11759935 PREVIOUSLY RECORDED ON REEL 040925 FRAME 0001. ASSIGNOR(S) HEREBY CONFIRMS THE RELEASE OF SECURITY INTEREST. Recorded Feb 17, 2020
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP, B.V. F/K/A FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 052917/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 11759915 AND REPLACE IT WITH APPLICATION 11759935 PREVIOUSLY RECORDED ON REEL 040928 FRAME 0001. ASSIGNOR(S) HEREBY CONFIRMS THE RELEASE OF SECURITY INTEREST. Recorded Jan 17, 2020
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP B.V.
Reel/Frame 052915/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 11759915 AND REPLACE IT WITH APPLICATION 11759935 PREVIOUSLY RECORDED ON REEL 037486 FRAME 0517. ASSIGNOR(S) HEREBY CONFIRMS THE ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS. Recorded Dec 10, 2019
From: CITIBANK, N.A.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 053547/0421 →
RELEASE OF SECURITY INTEREST Recorded Sep 10, 2019
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP B.V.
Reel/Frame 050744/0097 →
CORRECTIVE ASSIGNMENT TO CORRECT THE TO CORRECT THE APPLICATION NO. FROM 13,883,290 TO 13,833,290 PREVIOUSLY RECORDED ON REEL 041703 FRAME 0536. ASSIGNOR(S) HEREBY CONFIRMS THE THE ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS.. Recorded Feb 20, 2019
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: SHENZHEN XINGUODU TECHNOLOGY CO., LTD.
Reel/Frame 048734/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE NATURE OF CONVEYANCE PREVIOUSLY RECORDED AT REEL: 040632 FRAME: 0001. ASSIGNOR(S) HEREBY CONFIRMS THE MERGER AND CHANGE OF NAME. Recorded Sep 21, 2017
From: FREESCALE SEMICONDUCTOR INC.
To: NXP USA, INC.
Reel/Frame 044209/0047 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE PATENTS 8108266 AND 8062324 AND REPLACE THEM WITH 6108266 AND 8060324 PREVIOUSLY RECORDED ON REEL 037518 FRAME 0292. ASSIGNOR(S) HEREBY CONFIRMS THE ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS. Recorded Feb 1, 2017
From: CITIBANK, N.A.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 041703/0536 →
CHANGE OF NAME Recorded Nov 8, 2016
From: FREESCALE SEMICONDUCTOR, INC.
To: NXP USA, INC.
Reel/Frame 040632/0001 →
RELEASE OF SECURITY INTEREST Recorded Nov 7, 2016
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP B.V.
Reel/Frame 040928/0001 →
RELEASE OF SECURITY INTEREST Recorded Sep 21, 2016
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP, B.V., F/K/A FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 040925/0001 →
SUPPLEMENT TO THE SECURITY AGREEMENT Recorded Jun 16, 2016
From: FREESCALE SEMICONDUCTOR, INC.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 039138/0001 →
ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS Recorded Jan 13, 2016
From: CITIBANK, N.A.
To: MORGAN STANLEY SENIOR FUNDING, INC.
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ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS Recorded Jan 12, 2016
From: CITIBANK, N.A.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 037486/0517 →
PATENT RELEASE Recorded Dec 21, 2015
From: CITIBANK, N.A., AS COLLATERAL AGENT
To: FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 037356/0553 →
PATENT RELEASE Recorded Dec 21, 2015
From: CITIBANK, N.A., AS COLLATERAL AGENT
To: FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 037356/0143 →
PATENT RELEASE Recorded Dec 21, 2015
From: CITIBANK, N.A., AS COLLATERAL AGENT
To: FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 037354/0688 →
SECURITY AGREEMENT Recorded Nov 6, 2013
From: FREESCALE SEMICONDUCTOR, INC.
To: CITIBANK, N.A., AS NOTES COLLATERAL AGENT
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