Wireless communication unit, integrated circuit and biasing therefor
View Patent ↗A wireless communication unit comprises a semiconductor power amplifier device and a bias control circuit therefor. The bias control circuit comprises a detector for detecting at least a portion of the RF input signal; and a buffer for buffering the detected RF input signal. The detector is arranged to provide at least one inverted signal of the RF input signal. A semiconductor amplifier device is connected to an output of the bias control circuit and arranged to use an inverted detected signal to extract current from the output. When applied to a Doherty amplifier design, the biasing circuit requires fewer components, for example no video (buffer) amplifier and no delay block are required in the RF path. This facilitates integration of the circuit on a semiconductor die.
1. A wireless communication unit comprising:
a semiconductor power amplifier device for receiving a radio frequency (RF) input signal; and
a bias control circuit arranged to provide a bias voltage to the semiconductor power amplifier device that follows an envelope of the RF input signal, wherein the bias control circuit comprises:
a detector for detecting at least a portion of the RF input signal; and
a buffer for buffering the detected RF input signal;
wherein the detector is arranged to provide at least one inverted signal and one non-inverted signal of the RF input signal; and
wherein the bias control circuit comprises a third semiconductor amplifier device connected to an output of the bias control circuit and arranged to use an inverted detected signal to extract current from the output.
2. A wireless communication unit according to claim 1 wherein at least one inverted signal provided by the detector tracks envelope variations of the RF input signal.
3. A wireless communication unit according to claim 1 wherein the detector is a first semiconductor amplifier device that provides the at least one inverted signal to a gate port of the third semiconductor amplifier device.
4. A wireless communication unit according to any claim 1 , wherein the buffer is a second semiconductor amplifier device arranged to operate as a source or emitter follower.
5. A wireless communication unit according to claim 4 wherein the second semiconductor amplifier device is coupled serially to the third semiconductor amplifier device and arranged to provide a bias control signal to drive a low impedance capacitive load.
6. A wireless communication unit according to any claim 4 , wherein the third semiconductor amplifier device is coupled in parallel to a load attached to the bias control circuit output.
7. A wireless communication unit according to claim 1 , wherein a bias point of the third semiconductor amplifier device is tuned so that it is “off” when no RF input signal is applied.
8. A wireless communication unit according to claim 1 , wherein a capacitive connection couples the third semiconductor amplifier device and the first semiconductor amplifier device such that a bias point of the third semiconductor amplifier device is tuned “on” when the RF input signal decreases.
9. A wireless communication unit according to any claim 1 , wherein the first, second and third semiconductor amplifier devices are transistors that are of the same type as the semiconductor power amplifier device such that they are embedded in the same die.
10. A wireless communication unit according to claim 1 , wherein the semiconductor power amplifier device is configured within a Doherty amplifier.
11. A wireless communication unit according to claim 10 wherein the semiconductor power amplifier device biased by the bias control circuit functions as a peaking amplifier within the Doherty amplifier.
12. A radio frequency power amplifier integrated circuit comprising:
a semiconductor power amplifier device for receiving a radio frequency (RF) input signal; and
a bias control circuit arranged to provide a bias voltage to the semiconductor power amplifier device that follows an envelope of the RF input signal, wherein the bias control circuit comprises:
a detector for detecting at least a portion of the RF input signal; and
a buffer for buffering the detected RF input signal;
wherein the detector is arranged to provide at least one inverted signal and one non-inverted signal of the RF input signal; and
wherein the bias control circuit comprises a third semiconductor amplifier device connected to an output of the bias control circuit ( 465 ) and arranged to use an inverted detected signal to extract current from the output.
13. A radio frequency power amplifier integrated circuit according to claim 12 wherein the at least one inverted signal provided by the detector tracks envelope variations of the RF input signal.
14. A radio frequency power amplifier integrated circuit according to claim 12 wherein the detector is a first semiconductor amplifier device that provides the at least one inverted signal to a gate port of the third semiconductor amplifier device.
15. A radio frequency power amplifier integrated circuit according to claim 12 , wherein the buffer is a second semiconductor amplifier device arranged to operate as a source or emitter follower.
16. A radio frequency power amplifier integrated circuit according to claim 15 wherein the second semiconductor amplifier device is coupled serially to the third semiconductor amplifier device and arranged to provide a bias control signal to drive a low impedance capacitive load.
17. A wireless communication unit according to claim 12 , wherein the third semiconductor amplifier device is coupled in parallel to a load attached to the bias control circuit output.
18. A radio frequency power amplifier integrated circuit according to claim 12 , wherein a bias point of the third semiconductor amplifier device is tuned so that it is “off” when no RF input signal is applied.
19. A radio frequency power amplifier integrated circuit according to claim 12 , wherein a capacitive connection couples the third semiconductor amplifier device and the first semiconductor amplifier device such that a bias point of the third semiconductor amplifier device is tuned “on” when the RF input signal decreases.
20. A radio frequency power amplifier integrated circuit according to claim 12 , wherein the first, second and third semiconductor amplifier devices are transistors that are of the same type as the semiconductor power amplifier device such that they are embedded in the same die.
21. A radio frequency power amplifier integrated circuit according to claim 12 , wherein the semiconductor power amplifier device is configured within a Doherty amplifier.
22. A radio frequency power amplifier integrated circuit according to claim 21 wherein the semiconductor power amplifier device biased by the bias control circuit functions as a peaking amplifier within the Doherty amplifier.