Convolution operation in a multi-mode wireless processing system
View Patent ↗A system and method for performing a convolution operation in a multi-mode wireless processing system. The method can include loading an initial value and a stride value into an address generator, generating an address based on the initial value and the stride value, supplying the generated address to a series of memories, loading input data into a series of registers, multiplying the contents of each register with a value stored at the generated address in the memory associated with each register, adding up the resulting multiplication products, and generating output based on the resulting sum. The number of memories and registers are equal, each register having an associated memory.
1. A method for performing a convolution operation in a multi-mode wireless processing system, the method comprising:
loading an initial value and a stride value into an address generator;
generating an address based on the initial value and the stride value;
supplying the generated address to a series of memories;
loading input data into a series of registers, the series of registers being equal in number to the series of memories, each register being associated with one memory;
multiplying contents of each register with a value stored at the generated address in the memory associated with each register and generating a series of products;
adding the series of products and producing a product sum; and
generating an output stream from the product sum.
2. The method of claim 1 , wherein the generated address is initially set to the initial value.
3. The method of claim 1 , wherein the registers are flip-flop structures.
4. The method of claim 1 , wherein the memories are ROMs.
5. The method of claim 1 , wherein the multiplications of register contents with memory contents are performed in parallel.
6. The method of claim 1 , wherein the addition of products is performed by a complex adder tree.
7. The method of claim 1 , wherein a value R stored at an address A of the memory n is determined as follows:
R
A
,
n
=
round
(
sin
x
x
×
512
)
x
=
π
×
A
256
+
(
n
-
4
)
×
π
and A is defined for values 0 through 255.
8. The method of claim 1 , wherein there are eight memories and eight registers.
9. The method of claim 1 , further comprising:
performing subsequent multiplications between contents of each register and the value stored at the generated address in the memory associated with each register, the generated address being increased by the stride value in the subsequent multiplications;
adding the products of the subsequent multiplications and producing subsequent product sums; and
generating subsequent output streams based on the subsequent product sums.
10. The method of claim 9 , wherein the address generator increments the generated address by the stride value automatically.
11. The method of claim 1 , wherein loading the initial value and the stride value comprise loading the initial value and the stride value in response to a general purpose input output (GPIO) instruction.
12. A system for performing a convolution operation in a multi-mode wireless processing system, the system comprising:
an address generator comprising a first input to receive an initial value, a second input to receive a stride value and an output to provide an address based on the initial value and the stride value;
a series of memories;
a series of registers for storing an input value;
a series of complex multipliers, the series of multipliers, registers, and memories being equal in number, each multiplier being associated with one register and one memory, each multiplier generating a product of contents of the associated register and a value stored at the generated address in the associated memory; and
a complex adder tree for adding the series of products and producing a product sum.
13. The system of claim 12 , wherein the generated address is initially set to the initial value.
14. The system of claim 12 , wherein the registers are flip-flop structures.
15. The system of claim 12 , wherein the memories are ROMs.
16. The system of claim 12 , wherein the products generated by the complex multipliers are generated in parallel.
17. The system of claim 12 , wherein a value R stored at an address A of the memory n is determined as follows:
R
A
,
n
=
round
(
sin
x
x
×
512
)
x
=
π
×
A
256
+
(
n
-
4
)
×
π
and A is defined for values 0 through 255.
18. The system of claim 12 , wherein there are eight multipliers, memories, and registers.
19. The system of claim 12 , wherein the address generator increments the generated address by the stride value automatically.
20. The system of claim 12 , wherein the first input is to receive the initial value in response to a general purpose input output (GPIO) instruction.