Discrete multi-tone (DMT) system and method that communicates a data pump data stream between a general purpose CPU and a DSP via a buffering scheme
View Patent ↗The apparatus and method herein splits the function of a digital subscriber line (DSL) modem data pump between a digital signal processor (DSP 106 ) and a general purpose host central processing unit (CPU 102 ). The DSP ( 106 ) handles all front end data pump processing such as interface to an analog front end ( 108 and 110 ), FFT processing, FEQ processing, QAM decoding, and bit formatting. The host CPU ( 102 ) handles all back end data pump processing such as DMT tone deordering, data deinterleaving, error detection and correcting, bit descrambling, CRC processing, and the like. In order to enable the DSP ( 106 ) and the CPU ( 102 ) to communicate with each other effectively, buffers ( 132 ) under the control of specialized buffer management methodology (FIG. 4 ) are used.
1. A digital signal processing method, comprising:
performing a first plurality of digital signal processing operations using a first processor in order to convert an incoming stream of TCP/IP packets into DMT data symbols;
performing a second plurality of digital signal processing operations using a second processor in order to convert the DMT data symbols into a plurality of multi-tone signals modulated in magnitude and phase; and
dynamically adjusting the workload of at least one of the first processor or the second processor during operation of the first and second processors by determining whether to reassign at least a portion of the first and second plurality of digital signal processing operations between the first processor and second processor.
2. A method as in claim 1 , wherein said step of performing the first plurality of digital signal processing operations using the first processor comprises:
assembling ATM data cells from TCP/IP packets.
3. A method as in claim 1 , further comprising:
providing a first mode of operation wherein the second processor dedicates X MIPS to processing the DMT data symbols; and
providing a second mode of operation wherein the second processor dedicates Y MIPS to processing the DMT data symbols, wherein Y is less than X.
4. A method as in claim 1 , wherein the second processor comprises a FIFO buffer for receiving the DMT data symbols from the first processor.
5. A method as in claim 1 , further comprising:
determining if the DMT data symbols correspond to real time content or non-real time content.
6. A method as in claim 5 , wherein said step of determining if the DMT data symbols correspond to real time content or non-real time content is performed by the second processor.
7. A method as in claim 5 , further comprising:
retransmitting at least a portion of the non-real time content if the DMT data symbols correspond to non-real time content.
8. A method as in claim 5 , further comprising:
discarding at least a portion of the real time content if the second processor misses a deadline for converting the DMT data symbols into the plurality of multi-tone signals modulated in magnitude and phase.
9. A digital signal processing method, comprising:
performing a first plurality of digital signal processing operations using a first processor in order to convert an incoming stream of digital information into a first digital format;
performing a second plurality of digital signal processing operations using a second processor in order to convert the first digital format into a second digital format; and
determining whether to reassign at least a portion of the first and second plurality of digital signal processing operations between the first processor and second processor in order to dynamically adjust a workload of at least one of the first processor or the second processor during operation of the first and second processors.
10. A method as in claim 9 , wherein the incoming stream of digital information comprises TCP/IP packets.
11. A method as in claim 9 , wherein said step of performing the first plurality of digital signal processing operations using the first processor comprises:
assembling ATM data cells from TCP/IP packets.
12. A method as in claim 9 , wherein the first digital format comprises DMT data symbols.
13. A method as in claim 9 , wherein the second digital format comprises a plurality of multi-tone signals modulated in at least one of magnitude or phase.
14. A method as in claim 9 , further comprising:
providing a first mode of operation wherein the second processor dedicates X MIPS to processing the first digital format; and
providing a second mode of operation wherein the second processor dedicates Y MIPS to processing the first digital format, wherein Y is less than X.
15. A method as in claim 9 , wherein the second processor comprises a FIFO buffer for receiving the first digital format from the first processor.
16. A method as in claim 9 , further comprising:
determining if the first digital format corresponds to real time content or non-real time content.
17. A method as in claim 16 , wherein said step of determining if the first digital format corresponds to real time content or non-real time content is performed by the second processor.
18. A method as in claim 16 , further comprising:
retransmitting at least a portion of the non-real time content if the first digital format corresponds to non-real time content.
19. A method as in claim 16 , further comprising:
discarding at least a portion of the real time content if the second processor misses a deadline for converting the first digital format into the second digital format.
20. A digital signal processing system, comprising:
a first processor which performs a first plurality of digital signal processing operations to convert an incoming stream of TCP/IP packets into DMT data symbols;
a second processor which performs a second plurality of digital signal processing operations to convert the DMT data symbols into a plurality of multi-tone signals modulated in magnitude and phase; and
circuitry which dynamically adjusts a workload of at least one of the first processor or the second processor during operation of the first and second processors by determining whether to reassign at least a portion of the first and second plurality of digital signal processing operations between the first processor and second processor.