IP Library Granted Patent US 7,567,782
Granted Patent B2
US 7,567,782 · App. 11/494,821 · Granted Jul 28, 2009

Re-configurable impedance matching and harmonic filter system

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Quick Facts
Patent No.
US 7,567,782
App. No.
11/494,821
Granted
Jul 28, 2009
Kind
B2
Abstract

Methods and apparatus are provided to enable a transceiver ( 200 ) or transmitter including a single PA line-up ( 210 ) to transmit signals having frequencies in two or more different frequency bands, and/or having two or more different modulation types, and/or having two or more different RF power levels. The single PA line-up includes at least one variable matching circuit ( 216 ) and a variable harmonic filter ( 240 ) to tune match and tune filter communication signals prior to transmission. The variable matching circuit and the variable harmonic filter each include at least one variable capacitive element ( 2160 and 2400 ) that switches ON/OFF depending on whether a low frequency signal or a high frequency signal is being transmitted. Each variable capacitive element includes separate direct current and radio frequency terminals to enable the single PA line-up to change signal modulation and/or RF power levels in addition to frequencies.

Claims (37)

1. An apparatus for matching signal impedance between a power amplifier line-up and an antenna, comprising:

a variable matching circuit having a first input, a first output, and at least a first variable capacitive element, wherein the first input is configured to receive signals from a power amplifier, the variable matching circuit is configured to selectively enable the first variable capacitive element to produce impedance-matched signals; and

a variable harmonic filter having a second input, a second output, and at least a second variable capacitive element, wherein the second input is coupled to the first output and configured to receive the impedance-matched signals, the variable harmonic filter is configured to selectively enable the second variable capacitive element to filter out undesirable harmonics of the impedance-matched signals, and the second output is configured to be coupled to the antenna.

2. The apparatus of claim 1 , wherein at least one of the first variable capacitive element and the second variable capacitive element comprises:

at least one direct current (DC) terminal; and

at least one radio frequency (RF) terminal separate from the DC terminal.

3. The apparatus of claim 1 , wherein the variable matching circuit is configured to selectively enable the first variable capacitance element and the variable harmonic filter is configured to selectively enable the second variable capacitive element such that the filtered, impedance-matched signal includes at least one of frequencies in a plurality of different frequency bands, a plurality of different modulation types, and a plurality of different RF power levels.

4. The apparatus of claim 3 , wherein the variable matching circuit is configured to selectively enable the first variable capacitance element and the variable harmonic filter is configured to selectively enable the second variable capacitive element such that the filtered, impedance-matched signal includes at least one of frequencies in a plurality of different frequency bands, and wherein a first frequency band is in the range of 824 MHz to 915 MHz, and a second frequency band is in the range of 1710 MHz to 1910 MHz.

5. The apparatus of claim 1 , wherein at least one of the first variable capacitive element and the second variable capacitive element is a micro-electro-mechanical systems (MEMS) capacitive element.

6. The apparatus of claim 5 , wherein at least one of the first variable capacitive element and the second variable capacitive element is a tunable MEMS capacitive element.

7. The apparatus of claim 6 , wherein at least one of the first variable capacitive element and the second variable capacitive element is a binary MEMS capacitive element.

8. A system for matching signal impedance between a power amplifier line-up and an antenna, comprising:

a first matching circuit comprising a first input, a first output, and at least a first capacitive element, wherein the input is configured to be coupled to a signal generator and receive a signal from the signal generator, the first matching circuit is configured to impedance match the signal to produce a first impedance-matched signal;

a driver comprising a second input and a second output, wherein the second input is coupled to the first output and configured to receive the first impedance-matched signal, the driver is configured to amplify the first impedance-matched signal to produce a first amplified, impedance-matched signal;

a second matching circuit comprising a third input, a third output, and at least a second capacitive element, wherein the third input is coupled to the second output and configured to receive the first amplified, impedance-matched signal, the second matching circuit is configured to impedance match the first amplified, impedance-matched signal to produce a second impedance-matched signal;

a power amplifier including a fourth input and a fourth output, wherein the fourth input is coupled to the third output and configured to receive the second impedance-matched signal, the power amplifier is configured to amplify the second impedance-matched signal to produce a second, amplified impedance-matched signal;

a variable matching circuit comprising a fifth input, a fifth output, and at least a first variable capacitive element, wherein the fifth input is configured to receive signals from the fourth output, the variable matching circuit is configured to selectively enable the first variable capacitive element to produce a third impedance-matched signal; and

a variable harmonic filter comprising a sixth input, a sixth output, and at least a second variable capacitive element, wherein the sixth input is coupled to the fifth output and configured to receive the third impedance-matched signal, the variable harmonic filter is configured to selectively enable the second variable capacitive element to filter out undesirable harmonics of the third impedance-matched signal to produce a filtered, third impedance-matched signal, and the sixth output is configured to be coupled to the antenna.

9. The system of claim 8 , wherein at least one of the first variable capacitive element and the second variable capacitive element comprises:

at least one direct current (DC) terminal; and

at least one radio frequency (RF) terminal separate from the DC terminal.

10. The system of claim 8 , wherein the variable matching circuit is configured to selectively enable the first variable capacitance element and the variable harmonic filter is configured to selectively enable the second variable capacitive element such that the filtered, third impedance-matched signal includes at least one of frequencies in a plurality of different frequency bands, a plurality of different modulation types, and a plurality of different RF power levels.

11. The apparatus of claim 10 , wherein the variable matching circuit is configured to selectively enable the first variable capacitance element and the variable harmonic filter is configured to selectively enable the second variable capacitive element such that the filtered, third impedance-matched signal includes at least one of frequencies in a plurality of different frequency bands, and wherein a first frequency band is in the range of 824 MHz to 915 MHz, and a second frequency band is in the range of 1710 MHz to 1910 MHz.

12. The system of claim 8 , wherein at least one of the first variable capacitive element and the second variable capacitive element is a micro-electro-mechanical systems (MEMS) capacitive element.

13. The system of claim 12 , at least one of the first variable capacitive element and the second variable capacitive element is a tunable MEMS capacitive element.

14. The system of claim 13 , wherein at least one of the first variable capacitive element and the second variable capacitive element is a binary MEMS capacitive element.

15. The system of claim 8 , wherein the first matching circuit, the driver, the second matching circuit, the power amplifier, the variable matching circuit, and the variable harmonic filter form a single line-up.

16. The system of claim 8 , wherein the first matching circuit is a second variable matching circuit comprising at least a third variable capacitive element.

17. The system of claim 16 , wherein the second matching circuit is a third variable matching circuit comprising at least a fourth variable capacitive element.

18. A method for transmitting a plurality of communication signals with different characteristics from a single power amplifier line-up comprising a variable matching circuit including a variable capacitive element to an antenna, the method comprising:

generating a plurality of signals including a low band frequency or a high band frequency;

turning ON the variable capacitive element when a first signal includes the low band frequency;

turning OFF the variable capacitive element when a second signal includes the high band frequency;

transmitting the first signal from the single power amplifier line-up to the antenna; and

transmitting the second signal from the single power amplifier line-up to the antenna.

19. The method of claim 18 , wherein the low band frequency is in the range of 824 MHz to 915 MHz and the high band frequency is in the range of about 1710 MHz to 1910 MHz.

20. The method of claim 19 , wherein the first signal and the second signal include different modulation types.

Assignments (12)
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 11759915 AND REPLACE IT WITH APPLICATION 11759935 PREVIOUSLY RECORDED ON REEL 040925 FRAME 0001. ASSIGNOR(S) HEREBY CONFIRMS THE RELEASE OF SECURITY INTEREST. Recorded Feb 17, 2020
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP, B.V. F/K/A FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 052917/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 11759915 AND REPLACE IT WITH APPLICATION 11759935 PREVIOUSLY RECORDED ON REEL 040928 FRAME 0001. ASSIGNOR(S) HEREBY CONFIRMS THE RELEASE OF SECURITY INTEREST. Recorded Jan 17, 2020
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP B.V.
Reel/Frame 052915/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 11759915 AND REPLACE IT WITH APPLICATION 11759935 PREVIOUSLY RECORDED ON REEL 037486 FRAME 0517. ASSIGNOR(S) HEREBY CONFIRMS THE ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS. Recorded Dec 10, 2019
From: CITIBANK, N.A.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 053547/0421 →
RELEASE OF SECURITY INTEREST Recorded Nov 7, 2016
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP B.V.
Reel/Frame 040928/0001 →
RELEASE OF SECURITY INTEREST Recorded Sep 21, 2016
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP, B.V., F/K/A FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 040925/0001 →
ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS Recorded Jan 12, 2016
From: CITIBANK, N.A.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 037486/0517 →
PATENT RELEASE Recorded Dec 21, 2015
From: CITIBANK, N.A., AS COLLATERAL AGENT
To: FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 037354/0854 →
PATENT RELEASE Recorded Dec 21, 2015
From: CITIBANK, N.A., AS COLLATERAL AGENT
To: FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 037354/0225 →
PATENT RELEASE Recorded Dec 21, 2015
From: CITIBANK, N.A., AS COLLATERAL AGENT
To: FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 037356/0143 →
PATENT RELEASE Recorded Dec 21, 2015
From: CITIBANK, N.A., AS COLLATERAL AGENT
To: FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 037356/0553 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jan 7, 2015
From: ZENITH INVESTMENTS, LLC
To: APPLE INC.
Reel/Frame 034749/0791 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Sep 4, 2014
From: FREESCALE SEMICONDUCTOR, INC.
To: ZENITH INVESTMENTS, LLC
Reel/Frame 033687/0336 →