Cache locking device and methods thereof
View Patent ↗A method and device for locking a cache line of a cache is disclosed. The method includes automatically changing a state of a cache line from a valid locked state to an invalid locked state in response to receiving an indication that a memory location external to the cache and corresponding to the cache line is associated with an access request by a processor or other data access module. Thus, the locked state of a cache line is maintained even after data in the locked cache line is invalidated. By maintaining the invalid locked state, the cache line is not available for reallocation by the cache. This allows locked cache lines that become invalidated to remain locked without additional software overhead to periodically determine whether the lock has been lost due to invalidation of the cache line.
1. A method, comprising:
receiving a first indication while a cache line at a cache is in a first state that a first memory location external to the cache corresponding to the cache line is associated with an access request, the first state indicating that the cache line is valid and locked; and
in response to receiving the first indication, automatically changing the state of the cache line from the first state to a second state indicating that the data at the cache line is invalid and locked, the cache line unavailable for allocation to a second memory location when the cache line is invalid and locked.
2. The method of claim 1 , further comprising in response to execution of a first instruction at a first processor, changing the state of the cache line from a third state indicating data at the cache line is valid and unlocked to the first state.
3. The method of claim 2 , wherein the first indication is received in response to execution of a second instruction at a second processor.
4. The method of claim 1 , wherein the first state further indicates that the data external to the cache has been modified.
5. The method of claim 1 , wherein the first indication is received in response to execution of a first instruction at a first processor.
6. The method of claim 1 , wherein the second state further indicates that the data is shared.
7. The method of claim 1 , wherein the second state further indicates that the data has been modified.
8. The method of claim 1 , further comprising automatically changing the state of the cache line from the second state back to the first state in response to execution of a second instruction at the first processor.
9. The method of claim 8 , wherein the second instruction is a store instruction.
10. The method of claim 1 , wherein automatically changing the state of the cache line from the first state to a the second state further comprises change the state of the cache line based on the state of a mode bit.
11. The method of claim 1 , further comprising automatically changing the state of the cache line from the second state to a third state in response to execution of a first instruction at the first processor, the third state indicating the cache line is invalid and unlocked.
12. The method of claim 11 , further comprising automatically changing the state of the cache line from the third state to the second state in response to execution of a second instruction at the first processor.
13. The method of claim 11 , further comprising automatically changing the state of the cache line from the third state to the first state in response to execution of a second instruction at the first processor.
14. The method of claim 1 , further comprising:
receiving an address associated with a store access at the cache;
receiving data associated with the store access; and
in response to determining that the cache line is in the second state and that the cache line is associated with the address, storing the data at the first cache line.
15. The method of claim 14 , further comprising in response to determining that the cache does not include any cache line associated with the address, determining an available cache line and storing the data at the available cache line.
16. The method of claim 15 , wherein determining an available cache line comprises determining that the cache line is not available in response to determining that the cache line is in the second state.
17. A device, comprising:
a processor;
a cache coupled to the processor, the cache comprising:
a data array configured to store a cache line;
a status module configured to store state information associated with the cache line;
an array control module coupled to the status module, the array control module configured to change the state information to a first state indicating the cache line is valid and locked in response to execution of a lock instruction at the processor, and configured to automatically change the state information to a second state from the first state, in response to receiving an indication that a first data location external to the cache and corresponding to the cache line is associated with an access request, the second state indicating that the data at the cache line is invalid and locked, the cache line unavailable for allocation to a second data location when the cache line is invalid and locked.
18. The device of claim 17 , wherein the array control module is configured to automatically change the state information from the second state to the first state in response to execution of a second instruction at the processor.
19. The device of claim 17 , wherein the array control module is configured to automatically change the state information from the second state to a third state indicating the cache line is invalid and unlocked in response to execution of a second instruction at the processor.
20. A method, comprising:
receiving a first indication while a cache line at a cache is in a first state that a first memory location external to the cache corresponding to the cache line is associated with an access request, the first state indicating that the cache line is valid and locked;
in response to receiving the first indication, automatically changing the state of the cache line based on a mode bit from the first state to a second state indicating that the data at the cache line is invalid and locked.