Continuous time noise shaping analog-to-digital converter
View Patent ↗A system for a continuous time noise shaping analog-to-digital converter (“ADC”) with a suppressed carrier pulse width modulated (“PWM”) quantizer is disclosed. In particular, a suppressed carrier feedback signal may expand the dynamic range of a sigma delta modulated ADC and enhance the stability of the noise shaping loop.
1. A system for performing analog-to-digital conversion (“ADC”) with a pulse width modulated (“PWM”) feedback signal comprising:
a summer receiving an input signal, at least one feedback signal and generating an output error signal;
a noise shaping filter coupled with the summer and configured to receive and filter the error signal;
a first quantizer coupled with the noise shaping filter and configured to receive the filtered error signal and generate a first PWM signal;
an inverter coupled with the noise shaping filter and configured to invert the filtered error signal; and
a second quantizer coupled with the inverter and configured to receive the inverted filtered error signal and generate a second PWM signal;
wherein the first PWM signal and the second PWM signal are fed back into the summer.
2. The system according to claim 1 wherein a duty ratio of the first PWM signal is complementary of a duty ration of the second PWM signal.
3. The system according to claim 1 further comprising:
a ramp wave input coupled with the first quantizer and the second quantizer;
wherein the ramp wave input includes a ramp wave signal that is input into the first quantizer and the second quantizer.
4. The system according to claim 1 further comprising:
a first flip-flop coupled with the first quantizer; and
a second flip-flop coupled with the second quantizer;
wherein the first flip-flop is configured to receive an output from the first quantizer and generate the first PWM signal, further wherein the second flip-flop is configured to receive an output from the second quantizer and generate the second PWM signal.
5. The system according to claim 4 wherein the first flip-flop and the second flip-flop are coupled with a quantization clock, and wherein the first flip-flop and the second flip-flop are d-q flip-flops.
6. The system according to claim 1 wherein the noise shaping filter is a third order transconductor-capacitor (“Gm-C”) filter.
7. The system according to claim 1 wherein the first PWM signal is complementary of the second PWM signal and a carrier energy of the first PWM signal substantially cancels a carrier energy of the second PWM signal in the summer.
8. The system according to claim 1 wherein the ADC is a sigma delta modulator.
9. An analog-to-digital converter comprising:
a summer configured to receive an input signal and at least one feedback signal and generate an error signal;
a plurality of quantizers each configured to receive the error signal and generate a pulse width modulated (“PWM”) feedback signals based on the error signal, wherein the PWM feedback signals are fed back into the summer as the at least one feedback signal; and
an inverter coupled with one of the plurality of quantizers and configured to invert the error signal inputted into that quantizer.
10. The converter according to claim 9 wherein the plurality of quantizers includes a first quantizer and a second quantizer, wherein the first quantizer generates a first PWM feedback signal and the second quantizer generates a second PWM feedback signal.
11. The converter according to claim 10 further comprising a first and second flip-flop coupled with the first and second quantizer respectively.
12. The converter according to claim 9 further comprising a summer coupled with the at least one quantizer and configured to generate the input signal.
13. The converter according to claim 9 wherein the PWM feedback signals include a first PWM signal outputted from a first quantizer and a second PWM signal outputted from a second quantizer, further wherein the first PWM feedback signal is complementary of the second PWM feedback signal and a carrier energy of the first PWM signal effectively cancels a carrier energy of the second PWM signal.
14. The converter according to claim 13 further comprising:
a filter coupled with at least one of the quantizers and configured to generate the input signal;
wherein the inverter is coupled with the filter and the filtered signal is inverted by the inverter before being input into the second quantizer.
15. The converter according to claim 9 further comprising:
a ramp wave input coupled with the at least one quantizer;
wherein the ramp wave input includes a ramp wave signal that is input into the at least one quantizer.
16. A method for converting an analog input signal to a digital output signal comprising:
receiving an input signal;
summing the input signal with feedback signals to generate an error signal;
generating the feedback signals based on the error signal with at least one quantizer;
inverting one of the feedback signals; and
combining the feedback signals including the inverted feedback signal with the input signal to adjust the error signal.
17. The method according to claim 16 , wherein the feedback signals are pulse width modulated and at least one of the feedback signals is the digital output signal.
18. The method according to claim 16 wherein each of the feedback signals are further generated by at least one flip-flop.
19. The method according to claim 16 further comprising:
quantizing the error signal;
generating a plurality of pulse width modulated (“PWM”) signals; and
feeding the plurality of PWM signals back to the input signal to be summed as the feedback signals.
20. The method according to claim 19 wherein the PWM signals are complementary.