IP Library Granted Patent US 7,208,919
Granted Patent B2
US 7,208,919 · App. 11/130,539 · Granted Apr 24, 2007

Method and apparatus for digitally regulating an output voltage using noise-shaped component selection

Assignee: Sigmatel, Inc.
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Quick Facts
Patent No.
US 7,208,919
App. No.
11/130,539
Granted
Apr 24, 2007
Kind
B2
Abstract

Provided is a digitally-controlled linear regulator having noise-shaped component selection. The digitally-controlled linear regulator has a regulated-voltage sensor, a comparator module, a quantization module, and an impedance switching network. The regulated-voltage sensor is operably coupled to sense an output voltage of the digitally-controlled linear regulator to produce a sensed output voltage. The comparator module is operably coupled to compare the sensed output voltage with a reference voltage at a predetermined clock rate to produce a digital regulation signal. The quantization module is operably coupled to quantize the digital regulation signal to produce a quantized regulation signal. The impedance switching network is operably coupled to convert a source voltage into the output voltage of the digitally-controlled linear regulator based on the quantized regulation signal.

Claims (50)

1. A digitally-controlled linear regulator using noise-shaped component selection comprises:

a regulated-voltage sensor operably coupled to sense an output voltage of the digitally-controlled linear regulator to produce a sensed output voltage;

a comparator module operably coupled to compare the sensed output voltage with a reference voltage at a predetermined clock rate to produce a digital regulation signal;

a quantization module operably coupled to quantize the digital regulation signal to produce a quantized regulation signal; and

an impedance switching network operably coupled to convert a source voltage into the output voltage of the digitally-controlled linear regulator based on the quantized regulation signal.

2. The digitally-controlled linear regulator of claim 1 wherein the comparator module comprises:

a comparator operably coupled to compare the sensed output voltage with the reference voltage at the predetermined clock rate to produce a digital stream of comparison data; and

a loop filter operably coupled to the digital stream of comparison data to produce the digital regulation signal.

3. The digitally-controlled linear regulator of claim 2 wherein the quantization module is a sigma-delta modulator.

4. The digitally-controlled linear regulator of claim 1 wherein the impedance switching network comprises:

a selective resistive network to vary the impedance of the network based on the quantized regulation signal.

5. The digitally-controlled linear regulator of claim 1 wherein the impedance

switching network:

a fixed impedance; and

a switch that operably couples and decouples the fixed impedance between the source voltage and the output voltage based on the quantized regulation signal.

6. The digitally-controlled linear regulator of claim 1 wherein the impedance switching network comprises:

a plurality of gated current sources that are selectively activated and deactivated based on the quantized regulation signal.

7. The digitally-controlled linear regulator of claim 1 wherein the impedance switching network is a switched-capacitor network.

8. The digitally-controlled linear regulator of claim 1 is an integrated circuit.

9. A comprehensive system-on-a-chip comprises:

a processing core operably coupled to process input digital data and produce therefrom output digital data;

digital interface circuitry operable coupled to provide the input digital data to the processing core and to receive the output digital data from the processing core;

mixed signal circuitry operably coupled to convert input analog signals into the input digital data and to convert the output digital data into output analog signals; and

digital linear regulator circuitry operably coupled to convert a source voltage into a supply voltage that supplies at least one of: the processing core, the digital interface circuitry, and the mixed signal circuitry, wherein the digital linear regulator circuitry includes:

a regulated-voltage sensor operably coupled to sense an output voltage of the digitally-controlled linear regulator to produce a sensed output voltage;

a comparator module operably coupled to compare the sensed output voltage with a reference voltage at a predetermined clock rate to produce a digital regulation signal;

a quantization module operably coupled to quantize the digital regulation signal to produce a quantized regulation signal; and

an impedance switching network operably coupled to convert a source voltage into the output voltage of the digitally-controlled linear regulator based on the quantized regulation signal.

10. The comprehensive system-on-a-chip of claim 9 wherein the processing core is a digital signal processor.

11. The comprehensive system-on-a-chip of claim 9 wherein the comparator module further comprises:

a comparator operably coupled to compare the sensed output voltage with the reference voltage at the predetermined clock rate to produce a digital stream of comparison data; and

a loop filter operably coupled to the digital stream of comparison data to produce the digital regulation signal.

12. The comprehensive system-on-a-chip of claim 9 wherein the impedance switching network further comprises:

a selective resistive network between the source voltage and the output voltage to vary the impedance of the network based on the quantized regulation signal.

13. The comprehensive system-on-a-chip of claim 9 wherein the impedance switching network further comprises:

a plurality of gated current sources that are selectively activated and deactivated based on the quantized regulation signal.

14. The comprehensive system-on-a-chip of claim 9 wherein the impedance switching network further comprises:

a fixed impedance; and

a switch that operably couples and decouples the fixed impedance between the source voltage and the output voltage.

15. A method of digitally regulating a power source comprises:

sensing an output voltage by a regulated-voltage sensor to produce a sensed output voltage;

comparing the sensed output voltage with a reference voltage at a predetermined clock rate to produce a digital regulation signal;

quantizing the digital regulation signal to produce a quantized regulation signal; and

regulating a source voltage with the quantized regulation signal to provide the output voltage by operably coupling and decoupling an impedance of at least one of a plurality of selectable impedances between the source voltage and the output voltage in accordance with the quantized regulation signal.

16. The method of digitally regulating a power source of claim 15 wherein quantizing the digital regulation signal to produce a quantized regulation signal is performed by a sigma-delta modulator.

17. The method of digitally regulating a power source of claim 15 wherein regulating a source voltage further comprises:

enabling charging of an impedance element by the source voltage in accordance with the quantized regulation signal; and

enabling discharging of the impedance element to a load in accordance with the quantized regulation signal.

18. The method of digitally regulating a power source of claim 15 wherein regulating a source voltage further comprises:

operably coupling and decoupling a gated current source of a plurality of gated current sources between the source voltage and the output voltage in accordance with the quantized regulation signal.

Assignments (11)
CORRECTIVE ASSIGNMENT TO CORRECT THE ASSIGNEE NAME PREVIOUSLY RECORDED AT REEL: 037354 FRAME: 0773. ASSIGNOR(S) HEREBY CONFIRMS THE PATENT RELEASE. Recorded Aug 15, 2016
From: CITIBANK, N.A., AS COLLATERAL AGENT
To: SIGMATEL, LLC
Reel/Frame 039723/0777 →
PATENT RELEASE Recorded Dec 21, 2015
From: CITIBANK, N.A., AS COLLATERAL AGENT
To: SIGMATEL, INC.
Reel/Frame 037354/0734 →
PATENT RELEASE Recorded Dec 21, 2015
From: CITIBANK, N.A., AS COLLATERAL AGENT
To: SIGMATEL, INC.
Reel/Frame 037354/0773 →
PATENT RELEASE Recorded Dec 21, 2015
From: CITIBANK, N.A., AS COLLATERAL AGENT
To: SIGMATEL, INC.
Reel/Frame 037355/0838 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jan 7, 2015
From: ZENITH INVESTMENTS, LLC
To: APPLE INC.
Reel/Frame 034749/0791 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Sep 4, 2014
From: SIGMATEL, L.L.C.
To: ZENITH INVESTMENTS, LLC
Reel/Frame 033688/0862 →
SECURITY AGREEMENT Recorded Jun 17, 2013
From: SIGMATEL, LLC
To: CITIBANK, N.A., AS NOTES COLLATERAL AGENT
Reel/Frame 030628/0636 →
SECURITY AGREEMENT Recorded May 10, 2010
From: SIGMATEL, LLC
To: CITIBANK, N.A., AS NOTES COLLATERAL AGENT
Reel/Frame 024358/0439 →
SECURITY AGREEMENT Recorded Mar 16, 2010
From: SIGMATEL, LLC
To: CITIBANK, N.A.
Reel/Frame 024079/0406 →
SECURITY AGREEMENT Recorded Jul 9, 2008
From: SIGMATEL, INC.
To: CITIBANK, N.A.
Reel/Frame 021212/0372 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded May 17, 2005
From: MAY, MARCUS W.
To: SIGMATEL, INC.
Reel/Frame 016565/0726 →
Continuity (1)
Related Publication 20060261789A1 · Nov 23, 2006