Data processing system with peripheral access protection and method therefor
View Patent ↗One embodiment of the present invention provides a flexible peripheral access protection mechanism within a data processing system ( 10 ) in order to obtain a more secure operating environment. For example, the data processing system may include a combination of secure ( 12 ) and unsecure bus masters ( 14, 15 ) needing to access shared peripherals ( 22, 24 ). One embodiment allows for the dynamic update by a secure bus master ( 12 ) of access permissions corresponding to each unsecure bus master for each peripheral. A secure bus master is therefore able to establish which unsecure bus masters have permission to access which peripheral in order to protect the data processing system from corruption due to errant or hostile software running on unsecure bus masters. Through the use of a bus master identifier ( 36 ), access to the requested peripheral is either allowed or denied based on the permissions established by the secure bus master.
1. A method for providing peripheral access protection in a data processing system, comprising:
initiating a bus cycle which requires access to a peripheral, wherein the bus cycle is a read bus cycle;
providing a bus master identifier during at least a portion of the bus cycle;
using the bus master identifier to select read access control information for the bus cycle, wherein the read access control information defines read access permission to the peripheral;
determining if the access control information allows the bus master to access the peripheral;
initiating a second bus cycle which requires access to the peripheral, wherein the second bus cycle is a write cycle;
providing the bus master identifier during at least a portion of the second bus cycle;
using the bus master identifier to select write access control information for the second bus cycle, wherein the write access control information defines write access permission to the peripheral and is separate from the read access control information; and
determining if the write access control information allows the bus master to access the peripheral.
2. A method as in claim 1 , further comprising:
initiating a third bus cycle which requires access to the peripheral;
providing a second bus master identifier during at least a portion of the second bus cycle;
using the second bus master identifier to select second read or write access control information for the second bus cycle; and
determining if the second read or write access control information allows the second bus master to access the peripheral.
3. A method as in claim 2 , wherein the bus master identifier corresponds to the bus master and the second bus master identifier corresponds to the second bus master.
4. A method as in claim 1 , wherein each of the read and write access control information for the bus cycle is modifiable.
5. A method as in claim 4 , wherein each of the read and write access control information for the bus cycle is modifiable only once after reset.
6. A method as in claim 4 , wherein each of the read and write access control information for the bus cycle is modifiable by said bus master, and said bus master is a secured bus master, and the bus master identifier corresponds to said secured bus master.
7. A method as in claim 1 , further comprising:
if the access control information allows the bus master to access the peripheral, continuing the bus cycle and accessing the peripheral; and
if the access control information does not allow the bus master to access the peripheral, terminating the bus cycle before accessing the peripheral.
8. A method as in claim 7 , wherein said step of terminating the bus cycle comprises:
indicating that a bus error has occurred.
9. A method as in claim 1 , further comprising:
initiating a second bus cycle which requires access to another portion of the peripheral;
providing the bus master identifier during at least a portion of the second bus cycle;
using the bus master identifier and at least one address signal to select second access control information for the second bus cycle; and
determining if the second access control information allows the second bus master to access said another portion of the peripheral.
10. A method as in claim 1 , further comprising:
initiating a third bus cycle which requires access to a storage circuit which stores the access control information;
providing a second bus master identifier during at least a portion of the third bus cycle; and
determining if the second bus master identifier allows an access to the storage circuit which stores the access control information.
11. A method as in claim 10 , wherein the second bus master identifier allows the access to the storage circuit if the second bus master identifier corresponds to a secure bus master.
12. A method for providing peripheral access protection in data processing system, comprising:
initiating a bus cycle which requires access to peripheral;
providing a bus master identifier during at least a portion of the bus cycle;
using the bus master identifier to select access control information for the bus cycle;
determining if the access control information allows the bus master to access the peripheral, wherein the access control information for the bus cycle is modifiable, and wherein the access control information for the bus cycle is selectively modified in response to initiation of a software application executed by the data processing system, wherein the data processing system completes execution of the software application after the access control information for the bus cycle is selectively modified.
13. A method as in claim 12 , further comprising:
initiating a second bus cycle which requires access to a storage circuit which stores the access control information;
providing the bus master identifier during at least a portion of the second bus cycle; and
determining if the second bus master identifier allows an access to the storage circuit which stores the access control information.
14. A method as in claim 13 , wherein the second bus master identifier allows the access to the storage circuit if the second bus master identifier corresponds to a secure bus master.
15. The method as in claim 12 , wherein the access control information for the bus cycle is modifiable by said bus master, and said bus master is a secured bus master, and the bus master identifier corresponds to said secured bus master.
16. A method as in claim 12 further comprising:
if the access control information allows the bus master to access the peripheral, continuing the bus cycle and accessing the peripheral; and
if the access control information does not allow the bus master to access the peripheral terminating the bus cycle before accessing the peripheral.
17. A method as in claim 12 , further comprising:
initiating a second bus cycle which requires access to another portion of the peripheral;
providing the bus master identifier during at least a portion of the second bus cycle;
using the bus master identifier and at least one address signal to select second access control information for the second bus cycle; and
determining if the second access control information allows the second bus master to access said another portion of the peripheral.
18. A method as in claim 12 , further comprising:
initiating a second bus cycle which requires access to the peripheral;
providing a second bus master identifier during at least a portion of the second bus cycle;
using the second bus master identifier to select second access control information for the second bus cycle; and
determining if the second access control information allows the second bus master to access the peripheral.
19. A method as in claim 18 , wherein the bus master identifier corresponds to the bus master and the second bus master identifier corresponds to the second bus master.
20. A method as in claim 12 , wherein the access control information for the bus cycle is selectively modified in response to completion of a software application.