Coprocessor receiving target address to process a function and to send data transfer instructions to main processor for execution to preserve cache coherence
View Patent ↗A coprocessor ( 14 ) may be used to perform one or more specialized operations that can be off-loaded from a primary or general purpose processor ( 12 ). It is important to allow efficient communication and interfacing between the processor ( 12 ) and the coprocessor ( 14 ). In one embodiment, a coprocessor ( 14 ) generates and provides instructions ( 200, 220 ) to an instruction pipe ( 20 ) in the processor ( 12 ). Because the coprocessor ( 14 ) generated instructions are part of the standard instruction set of the processor ( 12 ), cache ( 70 ) coherency is easy to maintain. Also, circuitry ( 102 ) in coprocessor ( 14 ) may perform an operation on data while circuitry ( 106 ) in coprocessor ( 14 ) is concurrently generating processor instructions ( 200, 220 ).
1. A method for interfacing a processor to a coprocessor, wherein the processor is coupled to the coprocessor via a processor/coprocessor interface, the coprocessor capable of performing a plurality of coprocessor operations, comprising:
the processor performing an instruction fetch from a target address,
wherein the processor has a standard instruction set, and
wherein the standard instruction set of the processor comprises a plurality of opcodes;
in response to the processor performing the instruction fetch from the target address, the coprocessor initiating one of the plurality of coprocessor operations, wherein the one of the plurality of coprocessor operations is selected based on at least a portion of the target address;
the coprocessor using the target address to determine an opcode of a first instruction,
wherein the opcode of the first instruction is one of the plurality of opcodes of the standard instruction set of the processor;
the coprocessor transferring the first instruction to the processor;
the processor decoding and executing the first instruction to produce a result; and
the coprocessor receiving at least a portion of the result from the first instruction,
wherein the first instruction is within the standard instruction set of the processor and is not a special instruction related to the processor/coprocessor interface.
2. The method of claim 1 , further comprising:
prior to the processor performing the instruction fetch from the target address, the processor decoding an instruction which results in a change of flow to the target address.
3. The method of claim 2 , wherein the instruction which results in a change of flow to the target address is a branch instruction.
4. The method of claim 2 , wherein the instruction which results in a change of flow to the target address is a branch to subroutine instruction.
5. The method of claim 4 , further comprising:
the coprocessor, after initiating the one of the plurality of coprocessor operations completing the one of the plurality of coprocessor operations;
transferring to the processor a return from subroutine instruction; and
the processor decoding and executing the return from subroutine instruction.
6. The method of claim 1 , wherein the first instruction is a load instruction, and wherein the result from the first instruction is a data value retrieved during the load instruction.
7. The method of claim 1 , further comprising:
inserting the opcode of the first instruction received from the coprocessor into an instruction pipeline of the processor,
wherein the instruction pipeline of the processor is for pipelining the standard instruction set of the processor.
8. The method of claim 7 , wherein the second instruction comprises a change of flow instruction.
9. The method of claim 8 , wherein the second instruction results in a change of flow to an address following a first instruction address.
10. The method of claim 1 , further comprising:
after the coprocessor transfers the first instruction to the processor, the processor recognizing the opcode of the first instruction as one of the plurality of opcodes in the standard instruction set of the processor.