Digital audio system on a chip
View Patent ↗A GPIO cell of a SOC functions, in a first state, to pass an output signal from one of plurality of modules of the SOC to a pin when an output enable signal is activated. The GPIO cell further functions, in a second state, to pass an alternate output signal from another one of the plurality of modules of the SOC to the pin when the output enable signal is activated. The GPIO cell further functions, in a third state, to pass the output signal to the pin when an alternate output enable signal is activated. The GPIO cell further functions, in a fourth state, to pass the alternate output signal to the pin when the alternate output enable signal is activated. The GPIO cell further functions, when the output enable signal or the alternate output enable signal is deactivated, to receive an input signal from the pin.
1. A digital audio system on a chip (SOC) comprises:
a processing module;
random access memory for storing at least one of a program instruction and data;
read only memory for storing at least a portion of a boot algorithm;
universal serial bus (USB) interface operable to exchange a file with an external device;
an external memory interface operable to interface with a memory that stores at least one of a digital audio file and a digital video file;
at least one peripheral component interface;
a multimedia module operably coupled for at least one of:
providing an audio output from at least one of the digital audio file and the digital video file;
providing a video output from the digital video file;
receiving an audio input; and
receiving a video input;
a bus operably coupled to the processing module, the read only memory, the random access memory, the USB interface, the external memory interface, the at least one peripheral component interface, and the multimedia module; and
general purpose input/output (GPIO) module operably coupled to the bus, wherein the GPIO module includes a plurality of GPIO cells, wherein a GPIO cell of the plurality of GPIO cells is coupled to a pin of the digital audio SOC, and wherein the GPIO cell functions to:
in a first state, pass an output signal from one of the processing module, the USB interface, the external memory interface, the at least one peripheral component interface, and the multimedia module to the pin when an output enable signal is activated;
in a second state, pass an alternate output signal from another one of the processing module, the USB interface, the external memory interface, the at least one peripheral component interface, and the multimedia module to the pin when the output enable signal is activated;
in a third state, pass the output signal to the pin when an alternate output enable signal is activated;
in a fourth state, pass the alternate output signal to the pin when the alternate output enable signal is activated; and
when the output enable signal or the alternate output enable signal is deactivated, receive an input signal from the pin.
2. The digital audio SOC of claim 1 , wherein the at least one peripheral component interface comprises at least one of:
a CDROM drive, control buttons, switches, light emitting diode (LED) display, liquid crystal display (LCD) display, MMC/SC card, flash memory module, a RAM memory module, a two-wire interface module, hard drive, and a system packet interface module.
3. The digital audio SOC of claim 1 , wherein the GPIO cell comprises:
a register;
a first multiplexer;
a second multiplexer; and
an output driver operably coupled to the pin, wherein, when the GPIO cell is in the first state, the register stores a first digital value that causes the first multiplexer to provide the output signal to the output driver and causes the second multiplexer to provide the output enable signal to the output driver, wherein when the output enable signal is activated, the output driver is active.
4. The digital audio SOC of claim 3 , wherein the GPIO cell further comprises:
a second register that stores the alternate output signal, wherein, when the GPIO cell is in the second state, the register stores a second digital value that causes the first multiplexer to provide the alternate output signal to the output driver and causes the second multiplexer to provide the output enable signal to the output driver.
5. The digital audio SOC of claim 4 , wherein the GPIO cell further comprises:
a third register that stores the alternate output enable signal, wherein, when the GPIO cell is in the third state, the register stores a third digital value that causes the first multiplexer to provide the output signal to the output driver and causes the second multiplexer to provide the alternate output enable signal to the output driver.
6. The digital audio SOC of claim 5 , wherein, when the GPIO cell is in the fourth state, the GPIO cell further functions to:
store a fourth digital value in the register, wherein the fourth digital value causes the first multiplexer to provide the alternate output signal to the output driver and causes the second multiplexer to provide the alternate output enable signal to the output driver.
7. The digital audio SOC of claim 1 , wherein the GPIO cell comprises:
an input buffer operably coupled to the pin; and
a register operably coupled to the input buffer, wherein the input buffer provides the input signal to one of the register and a selected one of the processing module, the USB interface, the external memory interface, the at least one peripheral component interface, and the multimedia module.
8. A digital audio system on a chip (SOC) comprises:
a processing module;
random access memory for storing at least one of a program instruction and data;
read only memory for storing at least a portion of a boot algorithm;
universal serial bus (USB) interface operable to exchange a file with an external device;
an external memory interface operable to interface with a memory that stores at least one of a digital audio file and a digital video file;
a plurality of peripheral component interfaces;
a multimedia module operably coupled for at least one of:
providing an audio output from at least one of the digital audio file and the digital video file;
providing a video output from the digital video file;
receiving an audio input; and
receiving a video input;
a bus operably coupled to the processing module, the read only memory, the random access memory, the USB interface, the external memory interface, the plurality of peripheral component interfaces, and the multimedia module;
first general purpose input/output (GPIO) module operably coupled to the bus, wherein the first GPIO module includes a first plurality of GPIO cells, wherein a GPIO cell of the first plurality of GPIO cells is coupled to a first pin of the digital audio SOC, and wherein the GPIO cell of the first plurality of GPIO cells functions to:
in a first state, pass an output signal from the processing module to the first pin when an output enable signal is activated;
in a second state, pass an alternate output signal from one of the plurality of the peripheral component interfaces to the first pin when the output enable signal is activated;
in a third state, pass the output signal to the first pin when an alternate output enable signal is activated;
in a fourth state, pass the alternate output signal to the first pin when the alternate output enable signal is activated; and
when the output enable signal or the alternate output enable signal is deactivated, receive an input signal from the first pin; and
second general purpose input/output (GPIO) module operably coupled to the bus, wherein the second GPIO module includes a second plurality of GPIO cells, wherein a GPIO cell of the second plurality of GPIO cells is coupled to a second pin of the digital audio SOC, and wherein the GPIO cell of the second plurality of GPIO cells functions to:
in a first state, pass a second output signal from the processing module to the second pin when a second output enable signal is activated;
in a second state, pass a second alternate output signal from another one of the plurality of the peripheral component interfaces to the second pin when the second output enable signal is activated;
in a third state, pass the second output signal to the second pin when a second alternate output enable signal is activated;
in a fourth state, pass the second alternate output signal to the second pin when the second alternate output enable signal is activated; and
when the second output enable signal or the second alternate output enable signal is deactivated, receive a second input signal from the second pin.