Systems and methods of parallel to serial conversion
View Patent ↗A system and method for using one or more clock signals is disclosed. The system includes a clock translator that has a first input to receive a first reference clock signal and a second input to receive a second reference clock signal. The clock translator also includes an output to provide a bit rate clock signal having a clock frequency in a first ratio with respect to the frequency of the first reference clock but having a resolution based on at least a portion of the second reference clock signal. The second reference clock has a faster rate than the first reference clock.
1. A parallel to serial conversion system, comprising:
a sample rate converter to convert a sample rate of a digital input signal based on a sample rate control input;
a clock translator, including:
a first input to receive the sample rate control input;
a second input to receive a first reference clock signal;
a third input to receive a second reference clock signal;
an output to provide a bit rate clock signal having a clock frequency in a first ratio with respect to a frequency of the first reference clock signal and having a resolution based on at least a portion of the second reference clock signal; and
a parallel to serial converter to convert a parallel input to a serial output based on the bit rate clock signal.
2. The parallel to serial conversion system of claim 1 , further comprising:
a digital phase lock loop to provide the sample rate control input based on the first reference clock signal.
3. The parallel to serial conversion system of claim 1 , wherein the sample rate control input includes an integer portion and a fractional portion.
4. The parallel to serial conversion system of claim 1 , wherein the clock translator further includes an input module responsive to the first reference clock, an integrator responsive to the input module, and a delta-sigma modulator responsive to the integrator.
5. The parallel to serial conversion system of claim 4 , wherein the delta-sigma modulator is responsive to the sample rate control input.
6. The parallel to serial conversion system of claim 1 , wherein the first ratio is controlled by the sample rate control input.
7. The parallel to serial conversion system of claim 1 , wherein a rate of the first reference clock signal is asynchronous with respect to the second reference clock signal.
8. The parallel to serial conversion system of claim 1 , wherein the bit rate clock signal includes a plurality of pulses, and wherein the plurality of pulses and wherein a first set of the plurality of pulses are synchronized with edge transitions of the second reference clock signal.
9. The parallel to serial conversion system of claim 1 , wherein the second reference clock signal is at a faster rate than the first reference clock signal.
10. The parallel to serial conversion system of claim 1 , wherein the clock translator further comprises:
a first translation stage to calculate a second ratio between a rate of the second reference clock signal and a rate of the first reference clock signal; and
a second translation stage responsive to the first translation stage to provide the bit rate clock signal based on the sample rate control input.
11. The parallel to serial conversion system of claim 10 , wherein the second translation stage comprises an accumulator responsive to the first translation stage and a comparator responsive to the accumulator and to a reference value, wherein the accumulator is further responsive to the sample rate control input when the comparator indicates a favorable condition of the accumulator with respect to the reference value.
12. The parallel to serial conversion system of claim 11 , wherein the reference value is zero.
13. A method of providing a bit stream signal, the method comprising:
generating a bit stream signal having a plurality of bit transitions, wherein the plurality of bit transitions have a frequency in a first ratio with respect to the frequency of a first clock signal wherein a first set of the plurality of bit transitions have timing that is derived based on edges of a second clock signal; and
providing the generated bit stream signal.
14. The method of claim 13 , wherein the second clock signal has a faster rate than and is asynchronous with respect to the first clock signal.
15. The method of claim 13 , further comprising calculating a ratio between a rate of the second clock signal and a rate of the first clock signal; and generating the bit stream signal based on the ratio and based on a sample rate control input.
16. The method of claim 13 , further comprising providing the generated bit stream signal to a parallel to serial converter.
17. A method of converting a parallel data input to a serial data output, the method comprising:
receiving a parallel data input;
generating a bit stream signal having a plurality of bit transitions, wherein the plurality of bit transitions has a frequency in a first ratio with respect to the frequency of a first clock signal, and wherein a first set of the plurality of bit transitions has a timing that is derived based on selected edges of a second clock signal; and
converting the parallel data input to a serial data output based on the generated bit stream signal.
18. The method of claim 17 , further comprising converting a sample rate of the parallel data input based on a sample rate control signal.
19. The method of claim 17 , wherein the generated bit stream signal provides a high resolution input signal, and wherein the generated bit stream signal has intermediate edge transitions to provide enhanced resolution using an asynchronous second clock signal having a faster clock rate.
20. The method of claim 17 , wherein generating the bit stream signal includes calculating a second ratio between a rate of the second clock signal and a rate of the first clock signal and generating the bit stream signal based on a relationship between the second ratio and a sample rate control input.