IP Library Granted Patent US 6,906,591
Granted Patent B2
US 6,906,591 · App. 10/723,492 · Granted Jun 14, 2005

Amplifier having MOS capacitor compensation

View Patent ↗
Loading inventors, assignments & file history…
Monitor This Case
Get email alerts when status or documents change.
Order Certified Copies
Most orders are placed with the USPTO same day — all within 24 business hours.
Order via The Patent Place →
Pre-filled with this patent's details
Quick Facts
Patent No.
US 6,906,591
App. No.
10/723,492
Granted
Jun 14, 2005
Kind
B2
Abstract

An amplifier includes a transistor, a current source, a MOS capacitor, and a level shifting module. The transistor includes a gate, a drain, and a source, wherein the source of the transistor is operably coupled to a voltage node. The current source is operably coupled to provide a current to the drain of the transistor. The Metal Oxide Semiconductor (MOS) capacitor includes a gate, a drain, a source, and a well, wherein the drain, the well, and the source of the MOS capacitor are coupled together to form a first plate of the MOS capacitor and the gate of the MOS capacitor provides a second plate of the MOS capacitor, wherein the second plate of the MOS capacitor is operably coupled to the gate of the transistor, wherein the drain of the transistor provides an output for the amplifier and the gate of the transistor provides an input of the amplifier. The level shifting module is operably coupled to the first plate of the MOS capacitor such that the level shifting module shifts a gate-source voltage of the MOS capacitor to reduce variances of capacitance of the MOS capacitor such that bandwidth of the amplifier is limited and the amplifier is stable.

Claims (26)

1. An amplifier comprises:

a transistor having a gate, a drain, and a source, wherein the source of the transistor is operably coupled to a voltage node;

a current source operably coupled to provide a current to the drain of the transistor;

a Metal Oxide Semiconductor (MOS) capacitor having a gate, a drain, a source, and a well, wherein the drain, the well, and the source of the MOS capacitor are coupled together to form a first plate of the MOS capacitor and the gate of the MOS capacitor provides a second plate of the MOS capacitor, wherein the second plate of the MOS capacitor is operably coupled to the gate of the transistor, wherein the drain of the transistor provides an output for the amplifier and the gate of the transistor provides an input of the amplifier; and

a level shifting module operably coupled to the first plate of the MOS capacitor such that the level shifting module shifts a gate-source voltage of the MOS capacitor to reduce variances of capacitance of the MOS capacitor such that bandwidth of the amplifier is limited and the amplifier is stable.

2. The amplifier of claim 1 , wherein the level shifting module comprises:

a first transistor having a gate, a drain, and a source, wherein the gate of the first transistor is operably coupled to the drain of the transistor and the drain of the first transistor is operably coupled to a supply voltage; and

a current sink operably coupled to sink current from the source of the first transistor, wherein the source of the first transistor is operably coupled to the drain of the MOS capacitor.

3. The amplifier of claim 1 , wherein the level shifting module comprises:

a first transistor having a gate, a drain, and a source, wherein the gate of the first transistor is operably coupled to the drain of the transistor and the drain of the first transistor is operably coupled to a ground; and

a current source operably coupled to source current to the source of the first transistor, wherein the source of the first transistor is operably coupled to the drain of the MOS capacitor.

4. The amplifier of claim 1 , wherein the voltage node comprises at least one of a supply voltage and a ground.

5. An operational amplifier comprises:

input stage operably coupled to produce an output signal from a positive input signal and a negative input signal; and

an amplifier that includes:

a transistor having a gate, a drain, and a source, wherein the source of the transistor is operably coupled to a voltage node;

a current source operably coupled to provide a current to the drain of the transistor;

a Metal Oxide Semiconductor (MOS) capacitor having a gate, a drain, a source, and a well, wherein the drain, the well, and the source of the MOS capacitor are coupled together to form a first plate of the MOS capacitor and the gate of the MOS capacitor provides a second plate of the MOS capacitor, wherein the second plate of the MOS capacitor is operably coupled to the gate of the transistor, wherein the drain of the transistor provides an output for the amplifier and the gate of the transistor provides an input of the amplifier; and

a level shifting module operably coupled to the first plate of the MOS capacitor such that the level shifting module shifts a gate-source voltage of the MOS capacitor to reduce variances of capacitance of the MOS capacitor such that bandwidth of the amplifier is limited and the amplifier is stable.

6. The operational amplifier of claim 5 , wherein the level shifting module comprises:

a first transistor having a gate, a drain, and a source, wherein the gate of the first transistor is operably coupled to the drain of the transistor and the drain of the first transistor is operably coupled to a supply voltage; and

a current sink operably coupled to sink current from the source of the first transistor, wherein the source of the first transistor is operably coupled to the drain of the MOS capacitor.

7. The operational amplifier of claim 5 , wherein the level shifting module comprises:

a first transistor having a gate, a drain, and a source, wherein the gate of the first transistor is operably coupled to the drain of the transistor and the drain of the first transistor is operably coupled to a ground; and

a current source operably coupled to source current to the source of the first transistor, wherein the source of the first transistor is operably coupled to the drain of the MOS capacitor.

8. The operational amplifier of claim 5 , wherein the voltage node comprises at least one of a supply voltage and a ground.

Assignments (11)
CORRECTIVE ASSIGNMENT TO CORRECT THE ASSIGNEE NAME PREVIOUSLY RECORDED AT REEL: 037354 FRAME: 0773. ASSIGNOR(S) HEREBY CONFIRMS THE PATENT RELEASE. Recorded Aug 15, 2016
From: CITIBANK, N.A., AS COLLATERAL AGENT
To: SIGMATEL, LLC
Reel/Frame 039723/0777 →
PATENT RELEASE Recorded Dec 21, 2015
From: CITIBANK, N.A., AS COLLATERAL AGENT
To: SIGMATEL, INC.
Reel/Frame 037354/0734 →
PATENT RELEASE Recorded Dec 21, 2015
From: CITIBANK, N.A., AS COLLATERAL AGENT
To: SIGMATEL, INC.
Reel/Frame 037354/0773 →
PATENT RELEASE Recorded Dec 21, 2015
From: CITIBANK, N.A., AS COLLATERAL AGENT
To: SIGMATEL, INC.
Reel/Frame 037355/0838 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jan 7, 2015
From: ZENITH INVESTMENTS, LLC
To: APPLE INC.
Reel/Frame 034749/0791 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Oct 21, 2014
From: SIGMATEL, L.L.C.
To: ZENITH INVESTMENTS, LLC
Reel/Frame 033996/0485 →
SECURITY AGREEMENT Recorded Jun 17, 2013
From: SIGMATEL, LLC
To: CITIBANK, N.A., AS NOTES COLLATERAL AGENT
Reel/Frame 030628/0636 →
SECURITY AGREEMENT Recorded May 10, 2010
From: SIGMATEL, LLC
To: CITIBANK, N.A., AS NOTES COLLATERAL AGENT
Reel/Frame 024358/0439 →
SECURITY AGREEMENT Recorded Mar 16, 2010
From: SIGMATEL, LLC
To: CITIBANK, N.A.
Reel/Frame 024079/0406 →
SECURITY AGREEMENT Recorded Jul 9, 2008
From: SIGMATEL, INC.
To: CITIBANK, N.A.
Reel/Frame 021212/0372 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Nov 26, 2003
From: MAY, MICHAEL R.
To: SIGMATEL, INC.
Reel/Frame 014810/0940 →