Granted Patent B2

US 7,199,739 · App. 11/152,910 · Granted Apr 3, 2007

Abstract

Claims (43)

1. A programmable sample rate ADC, responsive to an input signal for producing an output signal having an output frequency, comprising:

a delta sigma modulator operably coupled to produce a digital signal from an input signal in accordance with a variable frequency clock signal;

a programmable decimation filter, operatively coupled to the digital signal and the control signal for producing the output signal, the programmable decimation filter including X stages of integration, a down-sampling stage for down-sampling by a factor of N, and Y stages of differentiation, wherein X is at least one, and wherein Y is at least one;

wherein the factor N is controlled, to control the output frequency to be substantially constant.

2. The programmable sample rate ADC of claim 1 wherein the output signal is operably coupled to a filter, the filter having at least one filter coefficient that is selected independent from the control signal.

3. A programmable sample rate ADC, responsive to an input signal for producing an output signal having an output frequency, comprising:

an analog to digital converter module, operatively coupled to the input signal and a variable frequency clock signal for producing a digital signal, the variable frequency clock signal having a clock frequency that is based on a control signal;

a programmable decimation filter, operatively coupled to the digital signal and the control signal for producing the output signal, wherein the programmable decimation filter includes a down-sampling stage for down-sampling by a factor of N that is controlled, based on the control signal;

wherein the output frequency is substantially constant.

4. The programmable sample rate ADC of claim 3 wherein the programmable decimation filter includes X stages of integration and wherein X is at least one.

5. The programmable sample rate ADC of claim 4 wherein the programmable decimation filter includes Y stages of differentiation and wherein X=Y.

6. The programmable sample rate ADC of claim 3 wherein the output signal is operably coupled to a filter, the filter having at least one filter coefficient that is selected independent from the control signal.

7. The programmable sample rate ADC of claim 6 wherein the analog to digital converter module includes a delta sigma modulator.

8. A method of converting an analog input signal into a digital output signal having an output sampling frequency that is substantially constant, the method comprising the steps of:

A–D converting the analog input signal into a digital signal by oversampling the analog input signal to produce a sequence of samples based on a variable frequency clock signal and converting the sequence of samples into a digital signal;

integrating the digital signal to produce an integrated signal;

down-sampling the integrated signal by a factor of N to produce a down-sampled signal; and

differentiating the down-sampled signal to produce the digital output signal;

wherein, the factor N is selected based on a control signal so as to provide the substantially constant output sampling frequency.

9. The method of claim 8 wherein the variable frequency clock signal has a clock frequency that is based on the control signal.

10. The method of claim 8 wherein the step of integrating includes integrating the digital signal X-times, wherein X is at least one.

11. The method of claim 10 wherein step of differentiating includes differentiating the down-sampled signal Y times, wherein Y is at least one.

12. The method of claim 11 wherein X=Y.

13. The method of claim 8 wherein the step of A–D converting includes delta sigma modulating the analog input signal.

14. A radio receiver front end for receiving a received radio signal having a plurality of channel signals, each of the plurality of channel signals being modulated at one of a corresponding plurality of carrier frequencies, and for converting a selected one of the plurality of channel signals into a digital baseband signal, the radio receiver front end comprising:

a channel selector, for producing a control signal that corresponds to a selected one of the plurality of channels;

a local oscillator, operatively coupled to a reference oscillation, for producing a local oscillation signal at a local oscillation frequency, the local oscillation frequency based on the control signal;

an analog to digital converter module, operatively coupled to a modulated signal, the modulated signal operably coupled to the receive radio signal, and a variable frequency clock signal for producing a digital signal; and

a programmable decimation filter, operatively coupled to the digital signal and the control signal for producing the digital baseband signal, wherein the programmable decimation filter includes a down-sampling stage for down-sampling by a factor of N that is controlled, based on the control signal.

15. The radio receiver front end of claim 14 wherein the programmable decimation filter includes X stages of integration and wherein X is at least one.

16. The radio receiver front end of claim 15 wherein the programmable decimation filter includes Y stages of differentiation and wherein Y is at least one.

17. The radio receiver front end of claim 16 wherein X=Y.

18. The radio receiver front end of claim 14 wherein the analog to digital converter module includes a delta sigma modulator.

19. The radio receiver front end of claim 14 further comprising a channel filter, operably coupled to the digital baseband signal, the channel filter having at least one filter coefficient that is selected independent from the selected one of the plurality of channels.

20. The radio receiver front end of claim 19 wherein the variable frequency clock signal is operably coupled to the local oscillation signal.

21. The radio receiver front end of claim 19 further comprising a divider module for producing the variable frequency clock signal based on the local oscillation signal.

22. The radio receiver front end of claim 14 wherein the IF signal includes an in-phase modulated signal and a quadrature-phase modulated signal, the digital signal includes an in-phase digital signal and a quadrature-phase digital signal and wherein, and the digital baseband signal includes an in-phase digital baseband signal and a quadrature-phase digital baseband signal.

23. The radio receiver front end of claim 22 wherein the ADC module includes a first ADC submodule for processing the in-phase component of the modulated signal into the in-phase digital signal and a second ADC submodule for processing the quadrature-phase component of the modulated signal into the quadrature-phase digital signal.

24. The radio receiver front end of claim 23 wherein the programmable decimation filter includes a first programmable decimation filter submodule for processing the in-phase component of the digital signal into the in-phase component baseband signal and a second first programmable decimation filter submodule for processing the quadrature-phase component of the digital signal into the quadrature-phase digital baseband signal.

25. The radio receiver front end of claim 14 further comprising a reference oscillator for producing the reference oscillation.

26. The radio receiver front end of claim 14 further comprising:

a low noise amplifier, operatively coupled to the received radio signal for producing an amplified radio signal; and

a mixing module, for mixing the amplified radio signal and the local oscillation signal to form the modulated signal.

Assignments (11)