System and method to establish an adjustable on-chip impedance
View Patent ↗A method to establish an adjustable on-chip impedance within a predetermined range that involves establishing a reference current for the adjustable on-chip impedance and applying this reference current to the adjustable on-chip impedance. A voltage produced by applying the reference current to the adjustable on-chip impedance is sensed and compared with the comparator or other similar processor to a reference voltage. This comparison allows the adjustable on-chip impedance to be tuned when the comparison of the sense voltage and the reference voltage is unfavorable. Tuning the impedance results in an impedance value within a predetermined range that accounts for variances of both the reference current and reference voltage.
1. A method to establish an adjustable on-chip impedance within a predetermined range, the method comprises:
establishing a reference current for the adjustable on-chip impedance;
sensing a voltage produced by applying the reference current to the adjustable on-chip impedance;
comparing the sensed voltage with a reference voltage; and
tuning the adjustable on-chip impedance when the comparison of the sensed voltage and the reference voltage is unfavorable, such that an impedance value of the adjustable on-chip impedance is within predetermined range that accounts for variance of the reference current and the reference voltage.
2. The method of claim 1 further comprises setting the impedance value of the adjustable on-chip impedance to an initial value prior to applying the reference current to the adjustable on-chip impedance.
3. The method of claim 2 , wherein the initial value of the adjustable on-chip impedance comprises at least one of a minimum impedance value, a maximum impedance value, and a nominal impedance value.
4. The method of claim 1 , wherein tuning the adjustable on-chip impedance further comprises:
changing the impedance value to produce an altered impedance value;
applying the reference current to the adjustable on-chip impedance having the altered impedance;
sensing the voltage produced by applying the reference current to the adjustable on-chip impedance having the altered impedance; and
comparing the sensed voltage with the reference voltage, wherein tuning the adjustable on-chip impedance continues when the comparison of the sensed voltage and the reference voltage is unfavorable.
5. The method of claim 1 , wherein tuning the adjustable on-chip impedance further comprises:
determining a voltage difference between the sensed voltage and the reference voltage; and
determining an impedance adjustment to the adjustable on-chip impedance based on the voltage difference.
6. The method of claim 1 , wherein comparing the sensed voltage with a reference voltage further comprises:
comparing the sensed voltage with a first reference voltage, wherein the first reference voltage corresponds to a low threshold of the range of acceptable impedance values; and
comparing the sensed voltage with a second reference voltage, wherein the second reference voltage corresponds to a high threshold of the range of acceptable impedance values.
7. The method of claim 1 , wherein the adjustable on-chip impedance corresponds to a termination resistor for universal serial bus (USB) transmit lines.
8. A calibration circuit to establish an impedance value of an adjustable on-chip impedance within a predetermined range, comprising:
a reference current source to provide a reference current, which is applied across the adjustable on-chip impedance;
a comparator operably coupled to sense and compare a voltage generated across the adjustable on-chip impedance, and a reference voltage, and wherein the comparator provides an output that indicates when the comparison of the sensed voltage and the reference voltage is unfavorable; and
a tuning module to receive the output of the comparator and to increment the adjustable on-chip impedance when the comparison of the sensed voltage and the reference voltage is unfavorable such that an impedance value of the adjustable on-chip impedance is within a predetermined range that accounts for variance of the reference current and the reference voltage.
9. The calibration circuit of claim 8 , wherein the reference current and reference voltage derive from a bandgap voltage reference.
10. The calibration circuit of claim 9 , wherein:
the tuning module changes the impedance value to produce an altered impedance value of the adjustable on-chip impedance to which the reference current is applied;
the comparator compares the sensed voltage produced by applying the reference current to the adjustable on-chip impedance and the reference voltage; and
wherein tuning module continues to change the adjustable on-chip impedance when the comparison of the sensed voltage and the reference voltage is unfavorable.
11. The calibration circuit of claim 8 , wherein the reference current source comprising a current mirror, which provides at least some of the variance of the reference current.
12. The calibration circuit of claim 8 , wherein the adjustable on-chip impedance corresponds to a termination resistor for universal serial bus (USB) transmit lines.