CPU powerdown method and apparatus therefor
View Patent ↗A CPU has a powerdown mode in which most of the circuitry does not receive power. Power-up, coming out of powerdown, is achieved in response to receiving an exception. Because most of the state information that is present in the CPU is not needed in response to an exception, there is no problem in removing power to most of the CPU during powerdown. The programmer's model register file and a few other circuits in the CPU are maintained in powerdown, but the vast majority of the circuits that make up the CPU: the execution unit, the instruction decode and control logic, instruction pipeline and bus interface, do not need to receive power. Removing power from these non-critical circuits results in significant power savings during powerdown. The powered circuits are provided with a reduced power supply voltage to provide additional power savings.
1. A data processing system on an integrated circuit, comprising:
a central processing unit (CPU) for executing instructions, including a low power mode instruction used for entering a low power mode;
wherein the CPU comprises an execution unit for executing instructions;
a logic unit for asserting a low power mode signal in response to the CPU entering a low power mode instruction;
a storage device for storing, prior to executing the low power mode instruction, a current state of a programmer's model; and
a bus interface for coupling the CPU to a system bus;
a clock generator for providing a clock signal to time various functions of the CPU;
a power control unit, coupled to the logic unit, the power control unit receiving the low power mode signal, and in response, the power control unit for disabling the clock generator, maintaining a power supply voltage to the logic unit and the storage device, while removing the power supply voltage from the execution unit and the bus interface;
wherein the central processing unit, the clock generator, and the power control unit are on the integrated circuit.
2. The data processing system of claim 1 , wherein the storage device includes a processor status register and an exception processor status register, wherein during low power mode, the processor status register is powered down and the exception processor status register is for receiving the power supply voltage and storing the information relating to the current status of the CPU during the low power mode.
3. The data processing system of claim 1 , wherein the storage device comprises:
a program counter for storing a current program count value during normal operation of the CPU; and
an exception program counter, coupled to the program counter, for storing the current program count value during the low power mode while the program counter is powered down.
4. The data processing system of claim 1 , wherein the power control unit has a first output for providing a first power supply voltage to the execution unit, and a second output for providing a second power supply voltage to the logic unit and the storage device, wherein during the low power mode, the first power supply voltage is reduced to about zero volts and the second power supply voltage is maintained at a normal operating voltage.
5. The data processing system of claim 4 , wherein the first power supply voltage is reduced to about zero volts and the second power supply voltage is reduced to an intermediate voltage level.
6. The data processing system of claim 4 , further comprising:
an instruction decode and control unit, coupled to the execution unit and to the first output of the power control unit for receiving the first power supply voltage; and
an instruction pipeline unit, coupled to the instruction decode and control unit and to the first output of the power control unit for receiving the first power supply voltage.
7. The data processor of claim 1 , wherein the logic unit will respond to an exception while the CPU is in the low power mode, and in response to receiving the exception, the exception logic unit providing a wakeup signal to the power control unit; and the power control unit for receiving the wakeup signal, and in response, the power control unit for restoring the power supply voltage to the execution unit, enabling the clock generator, and de-asserting the low power mode signal.
8. The data processing system of claim 7 , wherein the storage device further comprises:
a program counter for storing a current program count value during normal operation of the CPU; and
an exception program counter, coupled to the program counter, for receiving and storing the current program count value during low power mode of the CPU while the program counter is powered down during low power mode.
9. The data processing system of claim 7 , wherein the storage device further comprising:
a processor status register for storing current status information during normal operation of the CPU; and
an exception processor status register, coupled to the processor status register for receiving and storing the current status information during low power mode of the CPU while the processor status register is powered down during low power mode.
10. The data processing system of claim 7 , wherein the power control unit provides an awake signal to the logic unit after the power supply voltage is successfully restored to the execution unit.
11. A method for entering a low power mode in a data processing system on an integrated circuit having a central processing unit (CPU) that has a bus interface coupled to a system bus and an execution unit, the method comprising the steps of:
using a storage location within the CPU for maintaining a programmer's model of the CPU during a normal operation of the CPU including a time prior to the data processing system entering the low power mode;
executing an instruction that triggers entering the low power mode;
removing power in response to entering the low power mode from and keeping power removed during the low power mode from:
the bus interface; and
the execution unit;
maintaining power during the low power mode to:
the storage location so that a state of the programmer's model in the storage location prior to entering the low power mode is retained in the storage location during the low power mode; and
the logic unit.
12. The method of claim 11 , wherein the processor state information further includes processor status information, and a program count value.
13. The method of claim 12 , wherein the step of maintaining the current processor status further comprises storing the current processor state in a first shadow register.
14. The method of claim 12 , further comprising maintaining a current program count value in a second shadow register.
15. The method of claim 11 , wherein the instruction is characterized as being an instruction for stopping operation of the CPU.
16. The method of claim 11 , wherein the step of maintaining power is further characterized as applying power at a reduced voltage in response to entering the low power mode.
17. The method of claim 11 , further comprising the steps of:
detecting an exception condition while the CPU is in the low power mode;
asserting a wake up signal in response to detecting the exception condition;
restoring the power supply voltage to the predetermined portions of the CPU;
enabling the clock generator;
de-asserting the low power mode signal; and
initiating processing of the exception.
18. The method of claim 17 , further comprising the step of providing an awake signal to confirm that the power supply voltage is restored.
19. The method of claim 17 , wherein the current processor state information includes processor status information and the method further comprises the step of:
restoring the current processor status information from the predetermined location to a processor status register following the processing of the exception.
20. A data processing system on an integrated circuit comprising:
a central processing unit (CPU) for processing instructions including a stop instruction, wherein the CPU comprises:
an execution unit for the executing instructions;
a storage device for storing, prior to executing the stop instruction, a current state of a programmer's model; and
a storage device for storing information relating to a current state of the CPU prior to an execution of the stop instruction, wherein the information comprises the current state of a programmer's model;
a logic unit for asserting a low power mode signal in response to the CPU processing the stop instruction; and
a bus interface for coupling the CPU to a system bus;
a clock generator for generating a clock signal to time various functions of the CPU; and
a power control means, coupled to the logic unit, for receiving the low power mode signal and in response to receiving the low power mode signal disables the clock generator and maintains a power supply voltage to the logic unit and the storage device while removing the power supply voltage from the execution unit and the bus interface.