Selective cache line allocation instruction execution and circuitry
View Patent ↗A processing system and method performs allocation of memory cache lines in response to a cache write miss. A processor receives a plurality of data processing instructions. A first store instruction for storing data in a system memory at a predetermined address is decoded by decoding a first specifier within the first store instruction. The first specifier determines an allocation policy for the first store instruction wherein the allocation policy determines whether to store data within the cache when the predetermined address is not within the cache. Additional store instructions are decoded. For example, a second specifier determines an allocation policy for a second store instruction. The specifier in each of the store instructions may be implemented in various forms to provide a policy indicator for each store instruction. No allocation policy may also be established on a per-access basis.
1. A method, comprising:
providing a system memory, a storage device and a processor for receiving a plurality of data processing instructions; and
decoding a first store instruction for storing data in the system memory at a predetermined address by decoding a first specifier within the first store instruction, the first specifier determining an allocation policy for the first store instruction wherein the allocation policy determines whether to store the data within the storage device when the predetermined address is not within the storage device, and wherein the first specifier is provided as a bit within a displacement field of the first store instruction.
2. The method of claim 1 further comprising:
decoding a second store instruction within the plurality of data processing instructions by decoding a second specifier within the second store instruction, the second specifier determining the allocation policy for the second store instruction; and
setting a value of the second specifier different from the first specifier to make the allocation policy for the first store instruction to be different from the allocation policy for the second store instruction.
3. The method of claim 1 further comprising:
providing the first specifier within a predetermined field of the first store instruction.
4. The method of claim 1 further comprising:
providing the first specifier as a predetermined bit of the first store instruction.
5. The method of claim 1 further comprising:
providing the first specifier as a bit of a base register specifier of the first store instruction.
6. The method of claim 1 further comprising:
implementing the first specifier as a portion of the opcode of the first store instruction.
7. The method of claim 1 further comprising:
overriding a static default cache line allocation of the processor with the first specifier of the first store instruction.
8. The method of claim 1 wherein the first specifier establishes no cache line allocation for the processor.
9. A system comprising:
a processor;
a communication bus;
a system memory coupled to the processor via the communication bus; and
control circuitry coupled to the processor and system memory for decoding a first specifier within a first store instruction received by the processor, the first store instruction specifying an address in the system memory for storage of data, the first specifier determining an allocation policy wherein the allocation policy determines whether to store the data within the storage device when the address is not currently in the storage device, and wherein the first specifier is a bit within a displacement field of the first store instruction.
10. The system of claim 9 wherein the control circuitry decodes a second store instruction by decoding a second specifier within the second store instruction, the second specifier determining the allocation policy for the second store instruction independently from the allocation policy for the first store instruction.
11. The system of claim 10 wherein the second specifier is different from the first specifier to make the allocation policy for the first store instruction different from the allocation policy for the second store instruction.
12. The system of claim 9 wherein the first specifier is within a predetermined field of the first store instruction.
13. The system of claim 9 wherein the first specifier is a predetermined bit of the first store instruction.
14. The system of claim 9 wherein the first specifier is a bit of a base register specifier of the first store instruction.
15. The system of claim 9 wherein the first specifier is a portion of the opcode of the first store instruction.
16. The system of claim 9 wherein the first specifier of the first store instruction overrides a static default cache line allocation of the processor.
17. The system of claim 9 wherein the first specifier establishes no cache line allocation for the processor.
18. A method comprising:
providing a system memory and a cache memory;
coupling a processor to the system memory and the cache memory; and
executing a plurality of data processing instructions including a plurality of store instructions for storing information to the system memory, each of the plurality of store instructions including cache line allocation policy information for that associated store instruction that is provided as at least one bit within a displacement field of that associated store instruction, the cache line allocation policy information defining whether to store information in the cache memory when a storage address specified by any of the plurality of store instructions is not resident in the cache memory.