Bus arbitration in low power system
View Patent ↗Power is conserved in a data processing system that includes a processor core and system circuitry coupled to the processor core. A first method for conserving power includes entering a low power state by the processor and the system circuitry and enabling bus arbitration by the processor while the processor core remains in the low power state. One embodiment further contemplates a method of conserving power by granting bus access to a requesting device and entering a power conservation mode by the processor core in response thereto. Bus operations are then performed while the processor core remains in the power conservation mode. Another embodiment contemplates a method of debugging a data processing system in which a debug state is entered by the processor and the system circuitry and, thereafter, bus arbitration is enabled by the processor while the processor core remains in the debug state.
1. A method of debugging a data processing system, the data processing system including a processor and system circuitry coupled to the processor, the processor having a processor core, the method comprising:
entering a debug state by the processor and the system circuitry; and
enabling bus arbitration by the processor while the processor core remains in the debug state.
2. The method of claim 1 , wherein the enabling is performed in response to receiving a request for bus access from a bus requesting device.
3. The method of claim 2 , wherein the system circuitry comprises the bus requesting device.
4. The method of claim 2 , wherein the processor further comprises a processor clock controller coupled to the processor core, and wherein enabling bus arbitration comprises:
the processor clock controller providing a processor clock for a first duration during which a bus grant signal is provided to the bus requesting device.
5. The method of claim 4 , wherein after the first duration, enabling bus arbitration further comprises:
the processor clock controller holding the processor clock in a first configuration for a second duration during which the bus requesting device executes a bus operation.
6. The method of claim 5 , wherein the first duration is only as long as necessary for providing the bus grant signal.
7. The method of claim 1 , wherein the system circuitry comprises a system controller, and enabling bus arbitration comprises sending a first signal to the system controller.
8. The method of claim 7 , further comprising:
in response to the first signal, exiting the debug state by the system circuitry to enable bus operations of the bus requesting device.
9. The method of claim 8 , further comprising:
returning to the debug state by the system circuitry after completion of the bus operations, wherein returning to the debug state requires no software intervention.