Clock translator and parallel to serial converter
View Patent ↗A system and method for using one or more clock signals is disclosed. The system includes a clock translator that has a first input to receive a first reference clock signal and a second input to receive a second reference clock signal. The clock translator also includes an output to provide a bit rate clock signal having a clock frequency in a first ratio with respect to the frequency of the first reference clock but having a resolution based on at least a portion of the second reference clock signal. The second reference clock has a faster rate than the first reference clock.
1. A clock translator, comprising:
a first input to receive a first reference clock signal;
a second input to receive a second reference clock signal;
an output to provide a bit rate clock signal having a clock frequency in a first ratio with respect to a frequency of the first reference clock signal but having a resolution based on at least a portion of the second reference clock signal;
wherein the bit rate clock signal is provided to a parallel to serial converter.
2. The clock translator of claim 1 , wherein a rate of the first reference clock signal is asynchronous with respect to the second reference clock signal.
3. The clock translator of claim 1 , wherein the bit rate clock signal includes a plurality of pulses, and wherein the plurality of pulses have a frequency in a first ratio with respect to the frequency of the first reference clock signal and wherein a first set of the plurality of pulses are synchronized with edge transitions of the second reference clock signal.
4. The clock translator of claim 1 , wherein the second reference clock signal is at a faster rate than the first reference clock signal.
5. The clock translator of claim 1 , further comprising:
a third input to receive a sample rate control input, wherein the first ratio is controlled by the sample rate control input.
6. The clock translator of claim 5 , wherein the sample rate control input is a sample rate control input of a sample rate converter.
7. The clock translator of claim 5 , wherein the sample rate control input is provided by a digital phase lock loop.
8. The clock translator of claim 5 , further comprising:
a first translation stage to calculate a second ratio between a rate of the second reference clock signal and a rate of the first reference clock signal;
a second translation stage responsive to the first translation stage to provide the bit rate clock signal based on the sample rate control input.
9. The clock translator of claim 8 , wherein the first translation stage includes an input module responsive to the first reference clock signal and a low pass filter responsive to the input module.
10. The clock translator of claim 9 , wherein the low pass filter comprises an integrator, a feed forward value, and wherein the magnitude of the feed forward value is substantially subtracted from the integrator.
11. The clock translator of claim 8 , wherein the second translation stage includes a delta-sigma modulator responsive to the sample rate control input.
12. The clock translator of claim 11 , wherein the second translation stage comprises an accumulator responsive to the first translation stage, a comparator responsive to the accumulator and to a reference value, wherein the accumulator is further responsive to the sample rate control input when the comparator indicates a favorable condition of the accumulator with respect to the reference value.
13. The clock translator of claim 12 , wherein the reference value is zero.
14. A clock translator, comprising:
a first input to receive a first reference clock signal;
a second input to receive a second reference clock signal;
an output to provide a bit rate clock signal having a clock frequency in a first ratio with respect to a frequency of the first reference clock signal but having a resolution based on at least a portion of the second reference clock signal; and
a third input to receive a sample rate control input, wherein the first ratio is controlled by the sample rate control input.
15. The clock translator of claim 14 , wherein the sample rate control input is a sample rate control input of a sample rate converter.
16. The clock translator of claim 14 , wherein the sample rate control input is provided by a digital phase lock loop.
17. The clock translator of claim 14 , further comprising:
a first translation stage to calculate a second ratio between a rate of the second reference clock signal and a rate of the first reference clock signal;
a second translation stage responsive to the first translation stage to provide the bit rate clock signal based on the sample rate control input.
18. The clock translator of claim 17 , wherein the first translation stage includes an input module responsive to the first reference clock signal and a low pass filter responsive to the input module.
19. The clock translator of claim 18 , wherein the low pass filter comprises an integrator, a feed forward value, and wherein the magnitude of the feed forward value is substantially subtracted from the integrator.
20. The clock translator of claim 17 , wherein the second translation stage includes a delta-sigma modulator responsive to the sample rate control input.
21. The clock translator of claim 20 , wherein the second translation stage comprises an accumulator responsive to the first translation stage, a comparator responsive to the accumulator and to a reference value, wherein the accumulator is further responsive to the sample rate control input when the comparator indicates a favorable condition of the accumulator with respect to the reference value.
22. The clock translator of claim 21 , wherein the reference value is zero.
23. The clock translator of claim 14 , wherein a rate of the first reference clock signal is asynchronous with respect to the second reference clock signal.
24. The clock translator of claim 14 , wherein the bit rate clock signal includes a plurality of pulses, and wherein the plurality of pulses have a frequency in a first ratio with respect to the frequency of the first reference clock signal and wherein a first set of the plurality of pulses are synchronized with edge transitions of the second reference clock signal.
25. The clock translator of claim 14 , wherein the second reference clock signal is at a faster rate than the first reference clock signal.