Patent Assignment
Reel/Frame 034732/0019
Assignment of Assignor's Interest
Recorded: 2015-01-07
Pages: 32
Assignor
ZOZO MANAGEMENT, LLC
Executed: 2014-12-19
Assignee
APPLE INC.
1 INFINITE LOOP, CUPERTINO, CALIFORNIA, 95014
Covered Properties
(304)
For Forming an Integrated Circuit
Patent:
6,087,267 →
Application:
06/836,048 →
Integrated Circuit for Sensing an Environmental Condition and Producing a High Power Output
Application:
07/576,861 →
Method of Processing a Semiconductor Chip Package
Application:
07/767,593 →
Bus System Having a System Bus, an Internal Bus with Functional Units Coupled Therebetween and a Logic Unit for Use in Such System
Application:
07/803,819 →
Rotational Vibration Gyroscope
Patent:
5,377,544 →
Application:
07/810,043 →
Three Axes Accelerometer
Application:
07/810,063 →
Lead-On-Chip Semiconductor Device Having Peripheral Bond Pads
Application:
07/829,870 →
Method and Apparatus for Performing a Snoop-Retry Protocol in a Data Processing System
Application:
07/845,890 →
Structure and Method for Metallization of Semiconductor Devices
Application:
07/862,710 →
Ferromagnetic Memory Device and Method of Formation
Application:
07/873,139 →
Method and Apparatus for Preventing a Data Processing System from Entering a Non-Recoverable State
Application:
07/880,620 →
Laterally Sensitive Accelerometer and Method for Making
Patent:
5,337,606 →
Application:
07/926,616 →
Integrated Circuit for Sensing an Environmental Condition and Producing a High Power Circuit
Patent:
5,493,248 →
Application:
07/933,968 →
Distributed Capacitance Transmission Line
Application:
07/935,944 →
A Method for Forming an Interconnection Structure for Conductive Layers
Patent:
5,262,352 →
Application:
07/937,025 →
Phase Lock Loop Freqency Correction Circuit
Patent:
5,278,874 →
Application:
07/939,745 →
Laminated Semiconductor Wafer Structure and Method for Making and Using the Same in a Wafer Thinning Process
Application:
07/940,256 →
Method of Forming a Non-Selective Silicon-Germanium Epitaxial Film
Patent:
5,273,930 →
Application:
07/940,402 →
In a Data Processor a Method and Apparatus for Performing a Floating-Point Comparison Operation
Patent:
5,357,237 →
Application:
07/941,011 →
Semiconductor Device Including Very Low Sheet Resistivity Buried Layer
Patent:
5,283,454 →
Application:
07/943,642 →
High Speed, Low Gate/Drain Capacitance Dmos Device
Patent:
5,273,922 →
Application:
07/943,651 →
Data Slicer with Hold
Patent:
5,365,120 →
Application:
07/947,625 →
High-Speed Adder Using Varied Carry Scheme and Related Method
Application:
07/949,413 →
Current/Resistor Digital-to-Analog Converter Having Enhanced Integral Linearity and Method of Operation
Patent:
5,283,580 →
Application:
07/951,958 →
Digital Voltage Level Translator Circuit
Patent:
5,276,366 →
Application:
07/955,567 →
Method for Fabricating Bipolar Junction and Mos Transistors on Soi
Patent:
5,273,915 →
Application:
07/956,224 →
Leadframe Strip for Semiconductor Packages
Patent:
5,309,322 →
Application:
07/959,573 →
Voltage Limiter and Single-Ended to Differential Converter Using Same
Patent:
5,283,484 →
Application:
07/959,578 →
Method and Apparatus for Unstacking Registers in a Data Processing System
Patent:
5,640,548 →
Application:
07/962,560 →
Method of Forming Isolated Wells in the Fabrication of Bicmos Devices.
Patent:
5,268,312 →
Application:
07/964,700 →
Data Processing System for Generating Symmetrical Range of Addresses of Instructing-Address-Value with the Use of Inverting Sign Value
Patent:
5,386,534 →
Application:
07/967,295 →
Test Pattern Fault Equivalence
Patent:
5,410,548 →
Application:
07/967,311 →
Self-Doped Complementary Field Effect Transistor
Patent:
5,355,005 →
Application:
07/971,118 →
Method for Forming a Power Circuit Package
Application:
07/972,347 →
Apparatus and Method for Noise Reduction for a Full-Duplex Speakerphone or the Like
Patent:
5,410,595 →
Application:
07/975,348 →
Method for Forming Doped Regions Within a Semiconductor Substrate
Patent:
5,300,454 →
Application:
07/982,164 →
Lead-On-Chip Semiconductor Device and Method for Making the Same
Patent:
5,311,057 →
Application:
07/982,549 →
Lead Frame Assembly for Surface Mount Integrated Circuit Power Package
Application:
07/985,055 →
Method for Planarizing a Layer of Material
Patent:
5,272,117 →
Application:
07/986,303 →
Pressure Sensor Built into a Cable Connector
Patent:
5,341,684 →
Application:
07/986,411 →
Methods for Making and Using a Shallow Semiconductor Junction
Application:
07/987,870 →
Process Forming an Integrated Circuit
Patent:
5,377,139 →
Application:
07/990,341 →
Semiconductor Device Having Thin Package Body and Method for Making the Same
Patent:
5,294,827 →
Application:
07/991,548 →
Method for Forming a Transistor Having Silicided Regions
Patent:
5,352,631 →
Application:
07/991,801 →
Leveled Non-Coplanar Semiconductor Die Contacts
Patent:
5,296,736 →
Application:
07/993,563 →
Method for Thinning a Semiconductor Wafer
Patent:
5,268,065 →
Application:
07/993,984 →
High-Permittivity Dielectric Capacitor for Use in a Semiconductor Device and Process for Making the Same
Patent:
5,337,207 →
Application:
07/993,987 →
Method of Processing a Polycide Structure
Patent:
5,389,576 →
Application:
07/997,425 →
Flip Chip Package and Method of Making
Patent:
5,352,926 →
Application:
08/000,080 →
Method and Apparatus for Measuring the Topography of a Semiconductor Device
Patent:
5,338,932 →
Application:
08/000,168 →
Sigma-Delta Digital-to-Analog Converter with Reduced Noise
Patent:
5,323,157 →
Application:
08/004,816 →
Bipolar Transistor Apparatus with Iso-Terminals
Patent:
5,410,158 →
Application:
08/007,229 →
Power Efficient Transistor and Method Therefor
Patent:
5,546,040 →
Application:
08/007,230 →
Method for Fabricating Electrode Patterns
Patent:
5,395,740 →
Application:
08/010,224 →
Semiconductor Device Having a Ternary Boron Nitride Film and a Method for Forming the Same
Patent:
5,324,690 →
Application:
08/011,919 →
Method of Testing a Semiconductor Device Having a First Circuit Electrically Isolated from a Second Circuit
Patent:
5,381,105 →
Application:
08/017,159 →
Low Inductance Lead Frame for a Semiconductor Package
Patent:
5,309,019 →
Application:
08/023,407 →
Method for Rapidly Processing Floating-Point Operations Which Involve Exceptions
Patent:
5,341,320 →
Application:
08/024,011 →
Plasticland Grid Array Semiconductor Device and Method for Making the Same
Patent:
5,302,849 →
Application:
08/024,060 →
Method for Forming Metallization in an Integrated Circuit
Patent:
5,275,973 →
Application:
08/024,150 →
Charge Pump with Controlled Ramp Rate
Patent:
5,365,121 →
Application:
08/028,006 →
Flagless Semiconductor Device and Method for Making the Same
Application:
08/034,961 →
Method for Deriving a Piecewise Linear Model
Patent:
5,373,457 →
Application:
08/038,365 →
Method of Requesting Data and Apparatus Therefor
Application:
08/043,114 →
Method for Single Sided Polishing of a Semiconductor Wafer
Patent:
5,389,579 →
Application:
08/043,117 →
Scaled Reference Analog-to-Digital Conversion Circuitry and Method of Operation
Patent:
5,345,235 →
Application:
08/044,683 →
Method and Apparatus for Standby Recovery in a Phase Locked Loop
Patent:
5,339,278 →
Application:
08/044,790 →
Process for Fabricating Isolation Regions in a Semiconductor Device
Patent:
5,358,890 →
Application:
08/047,933 →
Current Controlled Variable Frequency Oscillator Having an Improved Operational Transconductance Amplifier
Patent:
5,564,089 →
Application:
08/049,938 →
Semiconductor Package Capable of Spreading Heat
Patent:
5,397,917 →
Application:
08/051,954 →
Polishing Pads Used to Chemical-Mechanical Polish a Semiconductor Substrate
Patent:
5,329,734 →
Application:
08/054,168 →
Optocoupler Package with Integral Voltage Isolation Barrier
Patent:
5,340,993 →
Application:
08/054,482 →
Probe for Providing Surface Images
Patent:
5,356,218 →
Application:
08/055,887 →
Piezoelectric Lead Zirconium Titanate Device and Method for Forming Same
Patent:
5,338,999 →
Application:
08/057,027 →
Electrical Interconnect and Method for Forming the Same
Application:
08/057,398 →
Planar Encapsulation Process
Application:
08/057,930 →
Integrated Circuit Pin Control Apparatus and Method Thereof in a Data Processing System
Patent:
5,457,802 →
Application:
08/061,474 →
Alignment Key for a Semiconductor Device Having a Seal Against Ionic Contamination
Patent:
5,311,061 →
Application:
08/063,474 →
Method of Doping a Semiconductor Substrate
Patent:
5,312,764 →
Application:
08/068,339 →
Tin Bismuth Solder Paste, and Method Using Paste to Form Connection Having Improved High Temperature Properties
Patent:
5,389,160 →
Application:
08/069,640 →
Process for Fabricating a Semiconductor Device Having a High Reliability Dielectric Material
Patent:
5,407,870 →
Application:
08/071,885 →
Lock Recovery Circuit for a Phase Locked Loop
Patent:
5,304,953 →
Application:
08/080,012 →
Semiconductor Material Contacting Member
Patent:
5,372,612 →
Application:
08/082,641 →
Voltage Controlled Oscillator Having a 50% Duty Cycle
Patent:
5,341,113 →
Application:
08/084,887 →
Encapsulated Electronic Component Having a Heat Diffusing Layer
Patent:
5,379,186 →
Application:
08/085,807 →
Ferroelectric Nonvolatile Random Access Memory Having Drive Line Segments
Patent:
5,373,463 →
Application:
08/086,254 →
Lock Detection Circuit for a Phase Lock Loop
Patent:
5,327,103 →
Application:
08/086,263 →
Phase Lock Loop with Self Test Circuitry and Method for Using the Same
Patent:
5,381,085 →
Application:
08/089,912 →
Apparatus for Detecting Completion of Energy Transfer in an Inductive Dc to Dc Converter
Patent:
5,463,306 →
Application:
08/093,488 →
A Ferromagnetic Memory Device
Patent:
5,329,486 →
Application:
08/096,204 →
Method for Making a Lead-on-Chip Semiconductor Device Having Peripheral Bond Pads
Patent:
5,455,200 →
Application:
08/097,505 →
Interconnection Structure for Conductive Layers and Method of Formation
Application:
08/098,925 →
Low-Power, Jitter-Compensated Phase Locked Loop and Method Therefor
Patent:
5,373,255 →
Application:
08/098,974 →
Cmos Driver Using Output Feedback Pre-Drive
Patent:
5,381,055 →
Application:
08/098,993 →
Method for Making a Substrate Structure with Improved Heat Dissipation
Patent:
5,354,717 →
Application:
08/099,682 →
Semiconductor Device with Diamond Heat Dissipation Layer
Application:
08/099,683 →
Amplifier with Feedback Having High Power Supply Rejection
Patent:
5,365,199 →
Application:
08/100,789 →
Digital Bus Data Retention
Patent:
5,511,170 →
Application:
08/100,815 →
Modular Low Voltage Filter with Common Mode Feedback
Patent:
5,345,190 →
Application:
08/100,830 →
Method and Apparatus for Generating Pseudorandom Numbers or for Performing Data Compression in a Data Processor
Patent:
5,416,783 →
Application:
08/103,614 →
Lead-On Chip Semiconductor Device Having Peripheral Bond Pads
Patent:
5,381,036 →
Application:
08/107,412 →
Diode Protected Semiconductor Device
Patent:
5,399,893 →
Application:
08/111,326 →
Curvature Correction Circuit for a Voltage Reference
Application:
08/112,917 →
A Complementary Heterojunction Device
Patent:
5,349,214 →
Application:
08/119,554 →
Method of Making Microelectronic Device Package Containing a Liquid
Patent:
5,413,965 →
Application:
08/119,555 →
Isolated Well and Method of Making
Patent:
5,394,007 →
Application:
08/119,636 →
Memory Efficient Gate Array Cell
Patent:
5,452,245 →
Application:
08/124,651 →
Method and Apparatus for Connection of Signals to an Integrated Circuit
Application:
08/124,786 →
Carbon Doped Silicon Semiconductor Device Having a Narrowed Bandgap Characteristic and Method
Patent:
5,360,986 →
Application:
08/131,541 →
Reset Signal Generation Circuit Having a Function for Protecting Write Data
Patent:
5,457,660 →
Application:
08/131,818 →
Method of Forming a Quantum Multi-Function Semiconductor Device
Patent:
5,371,038 →
Application:
08/139,180 →
Bandpass Sigma-Delta Analog-to-Digital Converter (Adc), Method Therefor, and Receiver Using Same
Patent:
5,442,353 →
Application:
08/140,948 →
Circuit and Method of Setting a Bias Point for a Single-Ended Amplifier During Power-Up
Patent:
5,329,246 →
Application:
08/140,950 →
Method of Cell Characterization for Energy Dissipation
Patent:
5,504,694 →
Application:
08/141,368 →
Acoustically Regulated Polishing Process
Patent:
5,399,234 →
Application:
08/143,020 →
Intergrated Circuit Test with Programmable Source for Both Ac and Dc Modes of Operation
Patent:
5,467,024 →
Application:
08/143,949 →
Electronic Device and Method for Making
Application:
08/143,959 →
Data Processor with Rename Buffer and Fifo Buffer for in-Order Instruction Completion
Application:
08/144,390 →
High Efficiency Class Ab Transconductance Amplifier
Patent:
5,337,007 →
Application:
08/147,235 →
Differential High Speed Track and Hold Amplifier
Application:
08/147,266 →
Method and Apparatus for Integrating a Plurality of Analog Input Signals Prior to Transmitting a Communications Signal
Patent:
5,634,202 →
Application:
08/149,486 →
Method of Cell Characterization in a Distributed Simulation System
Patent:
5,519,848 →
Application:
08/154,054 →
Electrical Contact and Method for Making an Electrical Contact
Patent:
5,446,247 →
Application:
08/154,576 →
Method and Apparatus for Performing Read Accesses from a Counter Which Avoid Large Rollover Error When Multiple Read Access Cycles Are Used
Patent:
5,566,322 →
Application:
08/154,774 →
Electronic Device Having Coplanar Heatsink and Electrical Contacts
Patent:
5,457,605 →
Application:
08/155,879 →
Package for Mating with a Semiconductor Die and Method of Manufacture
Application:
08/155,880 →
Temperature Stable Square Wave Oscillator
Patent:
5,386,201 →
Application:
08/157,545 →
Integrated Circuit Having an on Chip Thermal Circuit Requiring Only One Dedicated Integrated Circuit Pin and Method of Operation
Patent:
5,376,819 →
Application:
08/158,323 →
Method and Apparatus for Performing Parallel Zero Detection in a Data Processing System
Patent:
5,367,477 →
Application:
08/158,326 →
Method and Apparatus for Performing Multiplexed and Non-Multiplexed Bus Cycles in a Data Processing System
Patent:
5,483,660 →
Application:
08/158,584 →
Auto-Calibrated Current-Mode Digital-to-Analog Converter and Method Therefor
Patent:
5,446,455 →
Application:
08/160,645 →
Apparatus for Comparing the Weight of a Binary Word to a Number
Application:
08/161,848 →
A Ferrite-Semiconductor Resonator and Filter
Patent:
5,424,698 →
Application:
08/161,909 →
Method and Apparatus for Performing Frequency Tracking in an All Digital Phase Lock Loop
Patent:
5,381,116 →
Application:
08/165,682 →
Filtering Device for Use in a Phase Locked Loop Controller
Patent:
5,424,689 →
Application:
08/172,000 →
Process for Measuring Surface Topography Using Atomic Force Microscopy
Patent:
5,383,354 →
Application:
08/172,974 →
Artificial Neuron Using Adder Circuit and Method of Using Same
Patent:
5,548,685 →
Application:
08/176,604 →
Circuit and Method of Zero Generation in a Real-Time Filter
Patent:
5,394,036 →
Application:
08/176,971 →
Printed Circuit Board Comprising Elevated Bond Pads
Patent:
5,523,920 →
Application:
08/176,992 →
Single Metal-Plate Bypass Capacitor
Patent:
5,377,072 →
Application:
08/179,275 →
Chemical Vapor Deposition Trap with Tapered Inlet
Patent:
6,254,685 →
Application:
08/181,936 →
Process to Incorporate Nitrogen at an Interface of a Dielectric Layer in a Semiconductor Device
Patent:
5,464,792 →
Application:
08/186,957 →
Method for Thinning a Semiconductor Wafer
Patent:
5,476,566 →
Application:
08/187,363 →
Two's Complement Pulse Width Modulator and Method for Pulse Width Modulating a Two's Complement Number
Patent:
5,428,639 →
Application:
08/202,060 →
Adjustable Plating Cell for Uniform Bump Plating of Semiconductor Wafers
Patent:
5,391,285 →
Application:
08/202,210 →
Method for Making a Semiconductor Structure
Patent:
5,436,180 →
Application:
08/203,094 →
High Speed Adder Using a Varied Carry Scheme and Related Method
Patent:
5,375,081 →
Application:
08/206,288 →
Pipelined Memory Having Synchronous and Asynchronous Operating Modes
Patent:
5,384,737 →
Application:
08/207,509 →
Circuit for Providing a Voltage Ramp Signal
Patent:
5,502,410 →
Application:
08/212,750 →
Lead Frame Assembly for Surface Mount Integrated Circuit Power Package
Application:
08/215,000 →
Circuit and Method for Enhancing Logic Transitions Appearing on a Line
Patent:
5,510,739 →
Application:
08/218,283 →
A Method of Forming a Ferromgnetic Memory Device
Patent:
5,389,566 →
Application:
08/218,395 →
Methods for Making and Using a Shallow Semiconductor Junction
Patent:
5,384,269 →
Application:
08/221,546 →
Method for Capping Copper in Semiconductor Devices
Patent:
5,447,887 →
Application:
08/222,759 →
Comparator Having Latched Output When Disabled from the Power Supply
Patent:
5,488,320 →
Application:
08/223,400 →
A Power Circuit Package
Patent:
5,508,559 →
Application:
08/233,100 →
Method of Etching Copper Layers
Patent:
5,409,567 →
Application:
08/234,205 →
Electronic Module for Removing Heat from a Semiconductor Die
Patent:
5,565,705 →
Application:
08/235,992 →
Method for Connection of Signals to an Integrated Circuit
Patent:
5,501,006 →
Application:
08/239,796 →
Latching Ecl to Cmos Input Buffer Circuit
Patent:
5,426,381 →
Application:
08/247,819 →
Method for Coupling a Power Lead to a Bond Pad in an Electronic Module
Patent:
5,544,412 →
Application:
08/247,944 →
Piezoelectric Lead Zirconium Titanate Device and Method for Forming Same
Patent:
5,626,728 →
Application:
08/250,214 →
Antenna and Method for Forming Same
Patent:
5,528,254 →
Application:
08/251,444 →
Power-On Reset Circuit for Preventing Multiple Word Line Selections During Power-Up of an Integrated Circuit Memory
Patent:
5,477,176 →
Application:
08/253,076 →
Circuit and Method of Jtag Testing Multichip Modules
Patent:
5,568,492 →
Application:
08/254,846 →
Method for Forming a Power Circuit Package
Patent:
5,371,043 →
Application:
08/255,533 →
Short Circuit Detector for Sensors
Patent:
5,483,817 →
Application:
08/257,263 →
Method for Forming a Carbon Doped Silicon Semiconductor Device Having a Narrowed Bandgap Charateristic
Patent:
5,441,901 →
Application:
08/257,972 →
Pressure Sensor Package for Reducing Stress-Induced Measurement Error
Patent:
5,438,877 →
Application:
08/258,889 →
Logic Circuit with Negative Differential Resistance Device
Patent:
5,477,169 →
Application:
08/261,799 →
Method of Fabricating a Complementary Heterojunction Fet
Patent:
5,427,965 →
Application:
08/262,292 →
Method of Forming a Probe for an Atomic Force Microscope
Patent:
5,388,323 →
Application:
08/263,117 →
Artificial Neuron Using Adder Circuit and Method of Using Same
Patent:
5,581,661 →
Application:
08/269,243 →
Tuning Circuit for an Rc Filter
Patent:
5,625,316 →
Application:
08/269,509 →
Three Axes Accelerometer
Patent:
5,487,305 →
Application:
08/274,128 →
Method for Fabricating Electrode Patterns
Patent:
5,460,922 →
Application:
08/276,147 →
Address Generation Apparatus and Method Using a Peripheral Address Generation Unit and Fast Interrupts
Application:
08/278,204 →
Static-Random-Access Memory Cell and an Integrated Circuit Having a Static-Random-Access Memory Cell
Patent:
5,485,420 →
Application:
08/278,465 →
Method for Making a Self-Aligned Oxide Gate Cap
Patent:
5,504,039 →
Application:
08/282,351 →
Data Processing System Having a Compensation Circuit for Compensating for Capacitive Coupling on a Bus
Patent:
5,555,513 →
Application:
08/282,404 →
Process for Fabricating an X-Ray Absorbing Mask
Patent:
5,464,711 →
Application:
08/283,325 →
Semiconductor Device Interconnect Layout Structure for Reducing Premature Electromigration Failure Due to High Localized Current Density
Patent:
5,461,260 →
Application:
08/283,338 →
Rotational Vibration Gyroscope
Patent:
5,511,419 →
Application:
08/283,342 →
Circuit and Method of Reducing Sidetone in a Receive Signal Path
Patent:
5,649,008 →
Application:
08/284,950 →
An Interconnection Structure for Conductive Layers
Patent:
5,408,130 →
Application:
08/286,592 →
Method and Apparatus for Detecting Phase or Frequency Lock
Patent:
5,483,558 →
Application:
08/287,562 →
Flagless Semiconductor Device
Patent:
5,521,428 →
Application:
08/293,402 →
Integrated Circuit Having an on Chip Thermal Circuit Requiring Only One Dedicated Integrated Circuit Pin and Method of Operation
Patent:
5,477,076 →
Application:
08/297,280 →
Method and Apparatus for Decoding Information Within a Processing Device
Patent:
5,530,659 →
Application:
08/297,479 →
Programmable Pin Configuration Logic Circuit for Providing a Chip Select Signal and Related Method
Patent:
5,511,182 →
Application:
08/298,638 →
Dual Channel Small Outline Optocoupler Package and Method Thereof
Patent:
5,489,800 →
Application:
08/298,697 →
Tin Bismuth Solder Paste, and Method Using Paste to Form Connection Having Improved High Temperature Properties
Patent:
5,429,292 →
Application:
08/304,025 →
Bus System Having a System Bus, an Internal Bus with Functional Units Coupled Therebetween and a Logic Unit for Use in Such System
Patent:
5,499,338 →
Application:
08/320,590 →
Integrated Circuit Data Processor Which Provides External Sensibility of Internal Signals During Reset
Patent:
5,574,894 →
Application:
08/333,658 →
Method and Apparatus for a Regulated Supply on an Integrated Circuit
Patent:
5,563,779 →
Application:
08/349,291 →
An Electrical Interconnect and Method for Forming the Same
Patent:
5,480,835 →
Application:
08/350,395 →
Method and Apparatus for Preventing a Data Processing System from Entering a Non-Recoverable State
Patent:
5,546,588 →
Application:
08/350,396 →
Apparatus and Method for Inserting an Address in a Data Stream Through a Fifo Buffer
Application:
08/357,898 →
Amplifier Circuit Having High Lineraity for Cancelling Third Order Harmonic Distortion
Patent:
5,497,123 →
Application:
08/363,089 →
Data Processing System for Performing Efficient Fuzzy Logic Operations and Method Therefor
Patent:
5,671,332 →
Application:
08/363,196 →
Distributed Capacitance Transmission Line
Patent:
5,528,202 →
Application:
08/363,200 →
Optocoupler Package and Method for Making
Patent:
5,545,893 →
Application:
08/363,483 →
Microelectronic Device Packaging Containing a Liquid and Method
Patent:
5,477,084 →
Application:
08/367,628 →
Chemical-Mechanical-Polishing Pad Cleaning Process for Use During the Fabrication of Semiconductor Devices
Patent:
5,531,861 →
Application:
08/373,804 →
Lead Frame Assembly for Surface Mount Integrated Circuit Power Package
Application:
08/376,636 →
Method and Apparatus for Performing a Snoop-Retry Protocol in a Data Processing System
Patent:
5,506,971 →
Application:
08/386,252 →
Curvature Correction Circuit for a Voltage Reference
Patent:
5,479,092 →
Application:
08/388,116 →
Logic Gate Size Optimization Process for an Integrated Circuit Whereby Circuit Speed Is Improved While Circuit Area Is Optimized
Patent:
5,619,418 →
Application:
08/390,210 →
Differential High Speed Track and Hold Amplifier
Patent:
5,517,141 →
Application:
08/400,686 →
Method of Processing a Semiconductor Chip Package
Patent:
5,690,877 →
Application:
08/405,563 →
Method for Making a Semiconductor Device with Diamond Heat Dissipation Layer
Patent:
5,508,230 →
Application:
08/416,236 →
Method of Adjusting a Threshold Voltage for a Semiconductor Device Fabricated on a Semiconductor on Insulator Substrate
Patent:
5,532,175 →
Application:
08/423,614 →
Method and Apparatus for Designing an Integrated Circuit
Patent:
5,666,288 →
Application:
08/426,211 →
Structure and Method for Metallization of Semiconductor Devices
Patent:
5,554,889 →
Application:
08/430,105 →
Semiconductor Device with Improved Electromigration Resistance and Method for Making the Same
Patent:
5,506,450 →
Application:
08/435,107 →
Thermoplastic Interconnect for Electronic Device and Method for Making
Patent:
5,583,747 →
Application:
08/436,055 →
Data Processor with Rename Buffer and Fifo Buffer for in-Order Instruction Completion
Patent:
5,500,943 →
Application:
08/442,913 →
Method of Making a Ferrite/Semiconductor Resonator/Filter
Patent:
5,615,473 →
Application:
08/453,856 →
Small Outline Optocoupler Package Method
Patent:
5,677,245 →
Application:
08/454,471 →
Semiconductor Device Interconnect Layout Method and Structure for Reducing Permature Electromigration Failure Due to High Localized Current Density
Application:
08/472,602 →
Package for Mating with a Semiconductor Die
Patent:
5,587,605 →
Application:
08/473,833 →
Method for Pre-Shaping a Semiconductor Substrate for Polishing and Structure
Application:
08/494,510 →
Method for Designing a Signal Distribution Network
Patent:
5,724,557 →
Application:
08/499,838 →
Method for Pre-Shaping a Semiconductor Substrate for Polishing and Structure
Patent:
5,968,849 →
Application:
08/512,050 →
Updating Hierarchical Dag Representations Through a Bottom Up Method
Patent:
5,790,416 →
Application:
08/529,772 →
Process for Manufacturing a Package for Mating with a Bare Semiconductor Die
Patent:
5,589,402 →
Application:
08/550,416 →
Method for Testing Integrated Devices
Patent:
5,617,035 →
Application:
08/552,518 →
Method of Forming a Spacer
Application:
08/555,648 →
Lead Frame Assembly for Surface Mount Integrated Circuit Power Package
Patent:
5,587,883 →
Application:
08/557,667 →
Planar Encapsulation Process
Patent:
5,596,172 →
Application:
08/560,505 →
Apparatus for Comparing the Weight of a Binary Word to a Number
Patent:
5,623,519 →
Application:
08/591,191 →
Apparatus and Method for Automatically Placing Ties and Connection Elements Within an Integrated Circuit
Patent:
5,901,065 →
Application:
08/597,768 →
Method and Apparatus for Generating Instruction/Data Streams Employed to Verify Hardware Implementations of Integrated Circuit Designs
Patent:
5,774,358 →
Application:
08/625,153 →
Accurate Delay Prediction Based on Multi-Model Analysis
Patent:
5,751,593 →
Application:
08/629,487 →
Complementary Network Reduction for Load Modeling
Patent:
5,790,415 →
Application:
08/630,189 →
Method and Apparatus for Incorporating a Miller Compensation for Modeling Electrical Circuits
Patent:
5,796,985 →
Application:
08/639,393 →
Structure and Method for Metallization of Semiconductor Devices
Patent:
5,700,721 →
Application:
08/658,041 →
Method of Simulating an Integrated Circuit
Patent:
5,799,172 →
Application:
08/711,638 →
Method of Requesting Data by Interlacing Critical and Non-Critical Data Words of Multiple Data Requests and Apparatus Therefor
Patent:
5,668,975 →
Application:
08/722,694 →
An Interconnect Run Between a First Point and a Second Point in a Semiconductor Device for Reducing Electromigration Failure
Patent:
5,760,476 →
Application:
08/729,200 →
Automatic Synthesis of Standard Cell Layouts
Patent:
5,984,510 →
Application:
08/740,720 →
Automatic Layout Standard Cell Routing
Patent:
5,987,086 →
Application:
08/740,721 →
Method of Routing an Integrated Circuit
Patent:
6,006,024 →
Application:
08/740,768 →
Method for Generating a Reduced Order Model of an Electronic Circuit
Patent:
5,920,484 →
Application:
08/753,835 →
Platen Coating Structure for Chemical Mechanical Polishing and Method
Patent:
5,743,788 →
Application:
08/755,870 →
Mehtod for Optimizing Element Sizes in a Semiconductor Device
Patent:
5,903,471 →
Application:
08/805,862 →
Method for Determining Functional Equivalence Between Design Models
Patent:
5,754,454 →
Application:
08/808,759 →
Architectural Power Estimation Method and Apparatus
Patent:
5,940,779 →
Application:
08/810,876 →
Method for Optimizing Contact Pin Placement an Integrated Circuit
Patent:
6,075,934 →
Application:
08/848,907 →
Method of Chemical Mechanical Polishing (Cmp) Using an Underpad with Different Compression Regions and Polishing Pad Therefor
Patent:
5,899,745 →
Application:
08/887,695 →
Method for Verifying Protocol Conformance of an Electrical Interface
Patent:
5,966,306 →
Application:
08/888,588 →
Apparatus and Method for Inserting an Address in a Data Stream Through a Fifo Buffer
Patent:
5,889,948 →
Application:
08/906,608 →
Address Generation Apparatus and Method Using a Peripheral Address Generation Unit and Fast Interrupts
Patent:
5,761,690 →
Application:
08/910,359 →
Method of Forming a Spacer
Patent:
5,783,475 →
Application:
08/974,894 →
Method of Making a Semiconductor Device Using Chemical-Mechanical Polishing Having a Combination-Step Process
Patent:
5,985,748 →
Application:
08/980,782 →
Method of Forming Mask with Angled Struts of Reduced Height
Patent:
6,221,537 →
Application:
08/994,389 →
Method for Performing Model Checking in Integated Circuit Design
Patent:
5,999,717 →
Application:
09/001,751 →
Copper Interconnect Structure and Method of Formation
Patent:
6,174,810 →
Application:
09/055,510 →
Sparse-Carrier Devices and Method of Fabrication
Patent:
6,211,530 →
Application:
09/097,026 →
Pad Conditioner Coupling and End Effector for a Chemical Mechanical Planarization System and Method Therefor
Patent:
6,263,605 →
Application:
09/216,820 →
Semiconductor Structure Having a Crystalline Alkaline Earth Metal Oxide Interface with Silicon
Patent:
6,248,459 →
Application:
09/274,268 →
Process of Forming a Semiconductor Device
Patent:
6,165,567 →
Application:
09/290,385 →
Method and Apparatus for Integrated Circuit Design Verification
Patent:
6,321,186 →
Application:
09/303,995 →
Process for Forming High Aspect Ratio Circuit Features
Patent:
6,020,261 →
Application:
09/323,256 →
Verification of Design Blocks and Method of Equivalence Checking of Multiple Design Views
Patent:
6,378,112 →
Application:
09/332,817 →
Method for Forming a Dual Inlaid Copper Interconnect Structure
Patent:
6,326,301 →
Application:
09/352,134 →
Method for Fabricating a Semiconductor Structure with Reduced Leakage Current Density
Patent:
6,270,568 →
Application:
09/354,173 →
Method and Apparatus for Channel-Routing of an Electronic Device
Patent:
6,477,692 →
Application:
09/355,144 →
Modeling Method of Mosfet
Patent:
6,246,973 →
Application:
09/372,860 →
Method and Apparatus for Placing Repeaters in a Network of an Integrated Circuit
Patent:
6,493,854 →
Application:
09/411,725 →
Method for Fabricating a Semiconductor Structure Including a Metal Oxide Interface with Silicon
Application:
09/425,945 →
Method of Manufacturing a Semiconductor Component and Plating Tool Therefor
Patent:
6,361,675 →
Application:
09/451,552 →
Iterative, Noise-Sensitive Method of Routing Semiconductor Nets Using a Delay Noise Threshold
Patent:
6,480,998 →
Application:
09/551,322 →
Pad Conditioner Coupling and End Effector for a Chemical Mechanical Planarization System and Method Therefor
Patent:
6,514,126 →
Application:
09/586,189 →
Design Analysis Tool for Path Extraction and False Path Identification and Method Thereof
Method for Fabricating a Semiconductor Structure Including a Metal Oxide Interface with Silicon
Method and Apparatus for Analyzing Small Signal Response and Noise in Nonlinear Circuits
Method and Apparatus for Extracting a Portion of Data in a Source Register and Arranging It on One Side of a Destination Register
Method for Forming a Dual Inlaid Copper Interconnect Structure
Method for Generating Transition Delay Fault Test Patterns
Modeling Behavior of an Electrical Circuit
Method of Manufacturing a Semiconductor Component
Method and Apparatus for Measuring a Required Feature of a Layer During a Polishing Process
Design Verification System for Avoiding False Failures and Method Therefor
Method and Apparatus to Data Log at-Speed March C+ Memory Bist
Method for fabricating a semiconductor structure including a metal oxide interface with silicon
Application:
10/166,196 →
Publication:
US 2002/0146895
Method and Apparatus for Monitoring a Polishing Condition of a Surface of a Wafer in a Polishing Process
System and Method for Correlated Clock Networks
Pad Conditioner Coupling and End Effector for a Chemical Mechanical Planarization System and Method Therefor
Noise Analysis for an Integrated Circuit Model
Method and Apparatus for Constraint Graph Based Layout Compaction for Integrated Circuits
Patent:
7,086,027 →
Application:
10/332,111 →
Memory Management in a Data Processing System
Semiconductor Process and Composition for Forming a Barrier Material Overlying Copper
Method and Apparatus for Distortion Analysis in Nonlinear Circuits
Integrated Circuit Die Having a Copper Contact and Method Therefor
Accelerated Life Test of Mram Cells
Electromagnetic Noise Shielding in Semiconductor Packages Using Caged Interconnect Structures
Derivation of Circuit Block Constraints
Real-Time Debug Support for a Dma Device and Method Thereof
Patent:
6,920,586 →
Application:
10/764,110 →
Method for Making a Semiconductor Structure Using Silicon Germanium
Controlled Electroless Plating
Method of Making a Nitrided Gate Dielectric
Real-Time Debug Support for a Dma Device and Method Thereof
Controlled Electroless Plating
Related Assignments
(5)
Other recorded transfers of the patents in this record — the chain of ownership.
Assignment of Assignor's Interest
Oct 22, 2014
From: FREESCALE SEMICONDUCTOR, INC.
To: ZOZO MANAGEMENT, LLC
Reel/Frame 034034/0236 →
Assignment of Assignor's Interest
Oct 23, 2014
From: FREESCALE SEMICONDUCTOR, INC.
To: ZOZO MANAGEMENT, LLC
Reel/Frame 034038/0946 →
Patent Release
Dec 21, 2015
From: CITIBANK, N.A., AS COLLATERAL AGENT
To: FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 037354/0225 →
Patent Release
Dec 21, 2015
From: CITIBANK, N.A., AS COLLATERAL AGENT
To: FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 037356/0143 →
Patent Release
Dec 21, 2015
From: CITIBANK, N.A., AS COLLATERAL AGENT
To: FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 037356/0553 →