IP Library › Assignment 034038/0946
Patent Assignment
Reel/Frame 034038/0946

Assignment of Assignor's Interest

Recorded: 2014-10-23 Pages: 18
Assignor
FREESCALE SEMICONDUCTOR, INC.
Executed: 2012-06-29
Assignee
ZOZO MANAGEMENT, LLC
1209 ORANGE STREET, WILMINGTON, DELAWARE, 19801
Covered Properties (86)
For Forming an Integrated Circuit
Patent: 6,087,267 →
Application: 06/836,048 →
Test Pattern Fault Equivalence
Patent: 5,410,548 →
Application: 07/967,311 →
Chemical Vapor Deposition Trap with Tapered Inlet
Patent: 6,254,685 →
Application: 08/181,936 →
An Electrical Interconnect and Method for Forming the Same
Patent: 5,480,835 →
Application: 08/350,395 →
Logic Gate Size Optimization Process for an Integrated Circuit Whereby Circuit Speed Is Improved While Circuit Area Is Optimized
Patent: 5,619,418 →
Application: 08/390,210 →
Differential High Speed Track and Hold Amplifier
Patent: 5,517,141 →
Application: 08/400,686 →
Method for Making a Semiconductor Device with Diamond Heat Dissipation Layer
Patent: 5,508,230 →
Application: 08/416,236 →
Method of Adjusting a Threshold Voltage for a Semiconductor Device Fabricated on a Semiconductor on Insulator Substrate
Patent: 5,532,175 →
Application: 08/423,614 →
Method and Apparatus for Designing an Integrated Circuit
Patent: 5,666,288 →
Application: 08/426,211 →
Structure and Method for Metallization of Semiconductor Devices
Patent: 5,554,889 →
Application: 08/430,105 →
Semiconductor Device with Improved Electromigration Resistance and Method for Making the Same
Patent: 5,506,450 →
Application: 08/435,107 →
Thermoplastic Interconnect for Electronic Device and Method for Making
Patent: 5,583,747 →
Application: 08/436,055 →
Method of Making a Ferrite/Semiconductor Resonator/Filter
Patent: 5,615,473 →
Application: 08/453,856 →
Package for Mating with a Semiconductor Die
Patent: 5,587,605 →
Application: 08/473,833 →
Method for Designing a Signal Distribution Network
Patent: 5,724,557 →
Application: 08/499,838 →
Method for Pre-Shaping a Semiconductor Substrate for Polishing and Structure
Patent: 5,968,849 →
Application: 08/512,050 →
Updating Hierarchical Dag Representations Through a Bottom Up Method
Patent: 5,790,416 →
Application: 08/529,772 →
Process for Manufacturing a Package for Mating with a Bare Semiconductor Die
Patent: 5,589,402 →
Application: 08/550,416 →
Method for Testing Integrated Devices
Patent: 5,617,035 →
Application: 08/552,518 →
Lead Frame Assembly for Surface Mount Integrated Circuit Power Package
Patent: 5,587,883 →
Application: 08/557,667 →
Planar Encapsulation Process
Patent: 5,596,172 →
Application: 08/560,505 →
Apparatus and Method for Automatically Placing Ties and Connection Elements Within an Integrated Circuit
Patent: 5,901,065 →
Application: 08/597,768 →
Method and Apparatus for Generating Instruction/Data Streams Employed to Verify Hardware Implementations of Integrated Circuit Designs
Patent: 5,774,358 →
Application: 08/625,153 →
Accurate Delay Prediction Based on Multi-Model Analysis
Patent: 5,751,593 →
Application: 08/629,487 →
Complementary Network Reduction for Load Modeling
Patent: 5,790,415 →
Application: 08/630,189 →
Method and Apparatus for Incorporating a Miller Compensation for Modeling Electrical Circuits
Patent: 5,796,985 →
Application: 08/639,393 →
Method of Simulating an Integrated Circuit
Patent: 5,799,172 →
Application: 08/711,638 →
Automatic Synthesis of Standard Cell Layouts
Patent: 5,984,510 →
Application: 08/740,720 →
Automatic Layout Standard Cell Routing
Patent: 5,987,086 →
Application: 08/740,721 →
Method of Routing an Integrated Circuit
Patent: 6,006,024 →
Application: 08/740,768 →
Method for Generating a Reduced Order Model of an Electronic Circuit
Patent: 5,920,484 →
Application: 08/753,835 →
Platen Coating Structure for Chemical Mechanical Polishing and Method
Patent: 5,743,788 →
Application: 08/755,870 →
Mehtod for Optimizing Element Sizes in a Semiconductor Device
Patent: 5,903,471 →
Application: 08/805,862 →
Method for Determining Functional Equivalence Between Design Models
Patent: 5,754,454 →
Application: 08/808,759 →
Architectural Power Estimation Method and Apparatus
Patent: 5,940,779 →
Application: 08/810,876 →
Method for Optimizing Contact Pin Placement an Integrated Circuit
Patent: 6,075,934 →
Application: 08/848,907 →
Method of Chemical Mechanical Polishing (Cmp) Using an Underpad with Different Compression Regions and Polishing Pad Therefor
Patent: 5,899,745 →
Application: 08/887,695 →
Method for Verifying Protocol Conformance of an Electrical Interface
Patent: 5,966,306 →
Application: 08/888,588 →
Method of Forming a Spacer
Patent: 5,783,475 →
Application: 08/974,894 →
Method of Making a Semiconductor Device Using Chemical-Mechanical Polishing Having a Combination-Step Process
Patent: 5,985,748 →
Application: 08/980,782 →
Method of Forming Mask with Angled Struts of Reduced Height
Patent: 6,221,537 →
Application: 08/994,389 →
Method for Performing Model Checking in Integated Circuit Design
Patent: 5,999,717 →
Application: 09/001,751 →
Copper Interconnect Structure and Method of Formation
Patent: 6,174,810 →
Application: 09/055,510 →
Sparse-Carrier Devices and Method of Fabrication
Patent: 6,211,530 →
Application: 09/097,026 →
Pad Conditioner Coupling and End Effector for a Chemical Mechanical Planarization System and Method Therefor
Patent: 6,263,605 →
Application: 09/216,820 →
Semiconductor Structure Having a Crystalline Alkaline Earth Metal Oxide Interface with Silicon
Patent: 6,248,459 →
Application: 09/274,268 →
Process of Forming a Semiconductor Device
Patent: 6,165,567 →
Application: 09/290,385 →
Method and Apparatus for Integrated Circuit Design Verification
Patent: 6,321,186 →
Application: 09/303,995 →
Process for Forming High Aspect Ratio Circuit Features
Patent: 6,020,261 →
Application: 09/323,256 →
Verification of Design Blocks and Method of Equivalence Checking of Multiple Design Views
Patent: 6,378,112 →
Application: 09/332,817 →
Method for Forming a Dual Inlaid Copper Interconnect Structure
Patent: 6,326,301 →
Application: 09/352,134 →
Method for Fabricating a Semiconductor Structure with Reduced Leakage Current Density
Patent: 6,270,568 →
Application: 09/354,173 →
Method and Apparatus for Channel-Routing of an Electronic Device
Patent: 6,477,692 →
Application: 09/355,144 →
Modeling Method of Mosfet
Patent: 6,246,973 →
Application: 09/372,860 →
Method and Apparatus for Placing Repeaters in a Network of an Integrated Circuit
Patent: 6,493,854 →
Application: 09/411,725 →
Method of Manufacturing a Semiconductor Component and Plating Tool Therefor
Patent: 6,361,675 →
Application: 09/451,552 →
Iterative, Noise-Sensitive Method of Routing Semiconductor Nets Using a Delay Noise Threshold
Patent: 6,480,998 →
Application: 09/551,322 →
Pad Conditioner Coupling and End Effector for a Chemical Mechanical Planarization System and Method Therefor
Patent: 6,514,126 →
Application: 09/586,189 →
Design Analysis Tool for Path Extraction and False Path Identification and Method Thereof
Patent: 6,952,812 →
Application: 09/781,492 →
Publication: US 2002/0112213
Method for Fabricating a Semiconductor Structure Including a Metal Oxide Interface with Silicon
Patent: 6,709,989 →
Application: 09/885,409 →
Publication: US 2002/0197881
Method and Apparatus for Analyzing Small Signal Response and Noise in Nonlinear Circuits
Patent: 6,536,026 →
Application: 09/896,079 →
Publication: US 2003/0009732
Method and Apparatus for Extracting a Portion of Data in a Source Register and Arranging It on One Side of a Destination Register
Patent: 6,944,755 →
Application: 09/910,554 →
Publication: US 2004/0014427
Method for Forming a Dual Inlaid Copper Interconnect Structure
Patent: 6,551,919 →
Application: 09/970,284 →
Publication: US 2002/0039836
Method for Generating Transition Delay Fault Test Patterns
Patent: 6,651,227 →
Application: 09/986,211 →
Publication: US 2003/0079189
Modeling Behavior of an Electrical Circuit
Patent: 6,910,025 →
Application: 09/989,325 →
Publication: US 2003/0097348
Method of Manufacturing a Semiconductor Component
Patent: 6,726,826 →
Application: 10/011,329 →
Publication: US 2002/0040853
Method and Apparatus for Measuring a Required Feature of a Layer During a Polishing Process
Patent: 6,801,322 →
Application: 10/021,756 →
Publication: US 2003/0112451
Design Verification System for Avoiding False Failures and Method Therefor
Patent: 6,931,611 →
Application: 10/025,289 →
Publication: US 2003/0115562
Method and Apparatus to Data Log at-Speed March C+ Memory Bist
Patent: 6,944,806 →
Application: 10/155,897 →
Publication: US 2003/0221146
Method and Apparatus for Monitoring a Polishing Condition of a Surface of a Wafer in a Polishing Process
Patent: 6,709,312 →
Application: 10/180,740 →
Publication: US 2004/0002289
System and Method for Correlated Clock Networks
Patent: 6,925,622 →
Application: 10/260,251 →
Publication: US 2004/0064799
Noise Analysis for an Integrated Circuit Model
Patent: 7,093,223 →
Application: 10/304,423 →
Publication: US 2004/0103386
Method and Apparatus for Constraint Graph Based Layout Compaction for Integrated Circuits
Patent: 7,086,027 →
Application: 10/332,111 →
Memory Management in a Data Processing System
Patent: 6,925,542 →
Application: 10/393,592 →
Publication: US 2004/0186973
Semiconductor Process and Composition for Forming a Barrier Material Overlying Copper
Patent: 6,924,232 →
Application: 10/650,002 →
Publication: US 2005/0048773
Method and Apparatus for Distortion Analysis in Nonlinear Circuits
Patent: 7,007,253 →
Application: 10/657,304 →
Publication: US 2004/0083437
Integrated Circuit Die Having a Copper Contact and Method Therefor
Patent: 6,933,614 →
Application: 10/662,541 →
Publication: US 2004/0195696
Accelerated Life Test of Mram Cells
Patent: 6,894,937 →
Application: 10/672,959 →
Publication: US 2005/0068815
Electromagnetic Noise Shielding in Semiconductor Packages Using Caged Interconnect Structures
Patent: 6,933,599 →
Application: 10/694,146 →
Publication: US 2005/0087856
Derivation of Circuit Block Constraints
Patent: 7,039,883 →
Application: 10/728,622 →
Publication: US 2005/0125757
Real-Time Debug Support for a Dma Device and Method Thereof
Patent: 6,920,586 →
Application: 10/764,110 →
Method for Making a Semiconductor Structure Using Silicon Germanium
Patent: 7,195,963 →
Application: 10/851,347 →
Publication: US 2005/0260807
Controlled Electroless Plating
Patent: 7,176,133 →
Application: 10/994,720 →
Publication: US 2006/0110911
Method of Making a Nitrided Gate Dielectric
Patent: 7,402,472 →
Application: 11/067,257 →
Publication: US 2006/0194423
Real-Time Debug Support for a Dma Device and Method Thereof
Patent: 7,287,194 →
Application: 11/099,889 →
Publication: US 2005/0193256
Controlled Electroless Plating
Patent: 7,717,060 →
Application: 11/610,768 →
Publication: US 2007/0087566
Related Assignments (4)
Other recorded transfers of the patents in this record — the chain of ownership.
Assignment of Assignor's Interest Jan 7, 2015
From: ZOZO MANAGEMENT, LLC
To: APPLE INC.
Reel/Frame 034732/0019 →
Patent Release Dec 21, 2015
From: CITIBANK, N.A., AS COLLATERAL AGENT
To: FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 037354/0225 →
Patent Release Dec 21, 2015
From: CITIBANK, N.A., AS COLLATERAL AGENT
To: FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 037356/0143 →
Patent Release Dec 21, 2015
From: CITIBANK, N.A., AS COLLATERAL AGENT
To: FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 037356/0553 →