Method and apparatus to data log at-speed March C+ memory BIST

1. A method of testing a memory, comprising:

providing the memory with a Test Control and Observe wrapper, comprising:

a random access memory;

first and second multiplexers coupled to an output of the random access memory;

a flip-flop coupled to an output of the first multiplexer and to an input of the second multiplexer;

first and second logic gates coupled to an input of the flip-flop;

enabling a Built-in Self-test mode operation of the Test Control and Observe wrapper using the first logic gate;

utilizing the Test Control and Observe wrapper to test memory data by selecting a memory data via the first multiplexer; and

holding the memory data when a failure occurs using the second multiplexer, flip-flop and second logic gate.

2. The method of claim 1 , the random access memory comprising a static random access memory.

3. The method of claim 2 , the static random access memory comprising a static random access memory with a write through policy.

4. The method of claim 1 , further comprising utilizing the Test Control and Observe wrapper at functional speed.

5. The method of claim 1 , the step of holding the memory further comprising utilizing the memory data for memory bitmapping.

6. The method of claim 1 , further comprising utilizing the Test Control and Observe wrapper to bypass the memory during a scan mode operation.

7. The method of claim 1 , wherein enabling the Built-in Self-test mode operation includes executing a test algorithm.

8. The method of claim 7 , wherein enabling the Built-in Self-test mode operation includes executing a March algorithm.

9. The method of claim 8 , wherein enabling the Built-in Self-test mode operation includes executing a March C+ algorithm.

10. A method comprising:

providing a scan bypass wrapper comprising:

a reduction logic;

a random access memory coupled to the reduction logic;

first and second multiplexers coupled to an output of the random access memory;

a flip-flop coupled to an output of the first multiplexer and to an input of the second multiplexer;

first and second logic gates coupled to an input of the flip-flop;

utilizing the first multiplexer to select between a memory data of the random access memory and a bypass data of the reduction logic according to a Built-in Self-test mode signal;

utilizing the second logic gate to determine the mode of operation;

utilizing the second multiplexer to select between the memory data and a flip-flop data according to a mode of operation; and

utilizing the first logic gate to determine a hold condition for the flip-flop when a failure occurs.

11. The method of claim 10 , the first logic gate comprising an AND logic gate.

12. The method of claim 10 , the second logic gate comprising an OR logic gate.

13. An apparatus, comprising:

a processing unit;

a Built-in Self-test controller coupled to the processing unit;

a data circuit coupled to the Built-in Self-test controller;

an address circuit coupled to the Built-in Self-test controller;

a control circuit coupled to the Built-in Self-test controller;

a memory coupled to the data circuit, the address circuit and the control circuit;

a comparator circuit coupled to the memory and to the Built-in Self-test controller; and

a memory Test Control and Observe wrapper coupled to the memory comprising:

first and second multiplexers coupled to an output of the memory;

a flip-flop coupled to an output of the first multiplexer and to an input of the second multiplexer; and

first and second logic gates coupled to an input of the flip-flop.

14. The apparatus of claim 13 , wherein the memory includes a random access memory.

15. The apparatus of claim 14 , wherein the random access memory includes a static random access memory.

16. The apparatus of claim 15 , wherein the static random access memory includes a synchronous static random access memory.

17. The apparatus of claim 16 , wherein the synchronous static random access memory includes a synchronous static random access memory with a write-through policy.

18. The apparatus of claim 13 , wherein the memory Test Control and Observe wrapper is operable to perform a Built-in Self-test operation.

19. The apparatus of claim 13 , wherein the memory Test Control and Observe wrapper is operable to perform a memory bypass scan operation.

20. A memory Test Control and Observe wrapper, including:

a set of input signals;

a memory coupled to the set of input signals;

a reduction circuit coupled to the set of input signals;

a first multiplexer coupled to the reduction circuit, the memory, and a Built-in Self-test mode signal;

a first logic gate coupled to the Built-in Self-test mode signal and to a Built-in Self-test fail signal;

a flip-flop coupled to the first multiplexer and to the first logic gate;

a second multiplexer coupled to the memory and to the flip-flop;

a second logic gate coupled to the first logic gate, a scan mode signal and the second multiplexer;

a clock signal coupled to the memory and to the flip-flop; and

a data out signal coupled to the second multiplexer.

21. The apparatus of claim 20 wherein the memory is a random access memory.

22. The apparatus of claim 20 , wherein the first logic gate includes one or more logic gates for implementing an AND logic function, the one or more logic gates comprising a first input coupled to the Built-in Self-test mode signal and a second input coupled to a Built-in Self-test fail signal.

23. The apparatus of claim 20 , wherein the second logic gate includes one or more logic gates for implementing an OR logic function, the one or more logic gates comprising a first input coupled to the output of the first logic gate and a second input coupled to a scan mode signal.

24. The apparatus of claim 20 wherein the flip-flop includes a bank of flip-flops.

25. The apparatus of claim 24 wherein the bank of flip-flops is equal in width to a data output of the memory.