IP Library › Assignment 034034/0236
Patent Assignment
Reel/Frame 034034/0236

Assignment of Assignor's Interest

Recorded: 2014-10-22 Pages: 33
Assignor
FREESCALE SEMICONDUCTOR, INC.
Executed: 2012-08-14
Assignee
ZOZO MANAGEMENT, LLC
1209 ORANGE STREET, WILMINGTON, DELAWARE, 19801
Covered Properties (124)
Integrated Circuit for Sensing an Environmental Condition and Producing a High Power Circuit
Patent: 5,493,248 →
Application: 07/933,968 →
A Method for Forming an Interconnection Structure for Conductive Layers
Patent: 5,262,352 →
Application: 07/937,025 →
Phase Lock Loop Freqency Correction Circuit
Patent: 5,278,874 →
Application: 07/939,745 →
Method of Forming a Non-Selective Silicon-Germanium Epitaxial Film
Patent: 5,273,930 →
Application: 07/940,402 →
In a Data Processor a Method and Apparatus for Performing a Floating-Point Comparison Operation
Patent: 5,357,237 →
Application: 07/941,011 →
Semiconductor Device Including Very Low Sheet Resistivity Buried Layer
Patent: 5,283,454 →
Application: 07/943,642 →
High Speed, Low Gate/Drain Capacitance Dmos Device
Patent: 5,273,922 →
Application: 07/943,651 →
Data Slicer with Hold
Patent: 5,365,120 →
Application: 07/947,625 →
Current/Resistor Digital-to-Analog Converter Having Enhanced Integral Linearity and Method of Operation
Patent: 5,283,580 →
Application: 07/951,958 →
Method for Fabricating Bipolar Junction and Mos Transistors on Soi
Patent: 5,273,915 →
Application: 07/956,224 →
Leadframe Strip for Semiconductor Packages
Patent: 5,309,322 →
Application: 07/959,573 →
Voltage Limiter and Single-Ended to Differential Converter Using Same
Patent: 5,283,484 →
Application: 07/959,578 →
Method and Apparatus for Unstacking Registers in a Data Processing System
Patent: 5,640,548 →
Application: 07/962,560 →
Method of Forming Isolated Wells in the Fabrication of Bicmos Devices.
Patent: 5,268,312 →
Application: 07/964,700 →
Data Processing System for Generating Symmetrical Range of Addresses of Instructing-Address-Value with the Use of Inverting Sign Value
Patent: 5,386,534 →
Application: 07/967,295 →
Self-Doped Complementary Field Effect Transistor
Patent: 5,355,005 →
Application: 07/971,118 →
Apparatus and Method for Noise Reduction for a Full-Duplex Speakerphone or the Like
Patent: 5,410,595 →
Application: 07/975,348 →
Method for Forming Doped Regions Within a Semiconductor Substrate
Patent: 5,300,454 →
Application: 07/982,164 →
Lead-On-Chip Semiconductor Device and Method for Making the Same
Patent: 5,311,057 →
Application: 07/982,549 →
Method for Planarizing a Layer of Material
Patent: 5,272,117 →
Application: 07/986,303 →
Process Forming an Integrated Circuit
Patent: 5,377,139 →
Application: 07/990,341 →
Semiconductor Device Having Thin Package Body and Method for Making the Same
Patent: 5,294,827 →
Application: 07/991,548 →
Method for Forming a Transistor Having Silicided Regions
Patent: 5,352,631 →
Application: 07/991,801 →
Leveled Non-Coplanar Semiconductor Die Contacts
Patent: 5,296,736 →
Application: 07/993,563 →
High-Permittivity Dielectric Capacitor for Use in a Semiconductor Device and Process for Making the Same
Patent: 5,337,207 →
Application: 07/993,987 →
Sigma-Delta Digital-to-Analog Converter with Reduced Noise
Patent: 5,323,157 →
Application: 08/004,816 →
Bipolar Transistor Apparatus with Iso-Terminals
Patent: 5,410,158 →
Application: 08/007,229 →
Power Efficient Transistor and Method Therefor
Patent: 5,546,040 →
Application: 08/007,230 →
Semiconductor Device Having a Ternary Boron Nitride Film and a Method for Forming the Same
Patent: 5,324,690 →
Application: 08/011,919 →
Method for Rapidly Processing Floating-Point Operations Which Involve Exceptions
Patent: 5,341,320 →
Application: 08/024,011 →
Plasticland Grid Array Semiconductor Device and Method for Making the Same
Patent: 5,302,849 →
Application: 08/024,060 →
Method for Forming Metallization in an Integrated Circuit
Patent: 5,275,973 →
Application: 08/024,150 →
Charge Pump with Controlled Ramp Rate
Patent: 5,365,121 →
Application: 08/028,006 →
Method and Apparatus for Standby Recovery in a Phase Locked Loop
Patent: 5,339,278 →
Application: 08/044,790 →
Process for Fabricating Isolation Regions in a Semiconductor Device
Patent: 5,358,890 →
Application: 08/047,933 →
Current Controlled Variable Frequency Oscillator Having an Improved Operational Transconductance Amplifier
Patent: 5,564,089 →
Application: 08/049,938 →
Piezoelectric Lead Zirconium Titanate Device and Method for Forming Same
Patent: 5,338,999 →
Application: 08/057,027 →
Integrated Circuit Pin Control Apparatus and Method Thereof in a Data Processing System
Patent: 5,457,802 →
Application: 08/061,474 →
Alignment Key for a Semiconductor Device Having a Seal Against Ionic Contamination
Patent: 5,311,061 →
Application: 08/063,474 →
Method of Doping a Semiconductor Substrate
Patent: 5,312,764 →
Application: 08/068,339 →
Tin Bismuth Solder Paste, and Method Using Paste to Form Connection Having Improved High Temperature Properties
Patent: 5,389,160 →
Application: 08/069,640 →
Process for Fabricating a Semiconductor Device Having a High Reliability Dielectric Material
Patent: 5,407,870 →
Application: 08/071,885 →
Voltage Controlled Oscillator Having a 50% Duty Cycle
Patent: 5,341,113 →
Application: 08/084,887 →
Ferroelectric Nonvolatile Random Access Memory Having Drive Line Segments
Patent: 5,373,463 →
Application: 08/086,254 →
Method for Making a Lead-on-Chip Semiconductor Device Having Peripheral Bond Pads
Patent: 5,455,200 →
Application: 08/097,505 →
Low-Power, Jitter-Compensated Phase Locked Loop and Method Therefor
Patent: 5,373,255 →
Application: 08/098,974 →
Method for Making a Substrate Structure with Improved Heat Dissipation
Patent: 5,354,717 →
Application: 08/099,682 →
Amplifier with Feedback Having High Power Supply Rejection
Patent: 5,365,199 →
Application: 08/100,789 →
Digital Bus Data Retention
Patent: 5,511,170 →
Application: 08/100,815 →
Method and Apparatus for Generating Pseudorandom Numbers or for Performing Data Compression in a Data Processor
Patent: 5,416,783 →
Application: 08/103,614 →
Method of Making Microelectronic Device Package Containing a Liquid
Patent: 5,413,965 →
Application: 08/119,555 →
Isolated Well and Method of Making
Patent: 5,394,007 →
Application: 08/119,636 →
Carbon Doped Silicon Semiconductor Device Having a Narrowed Bandgap Characteristic and Method
Patent: 5,360,986 →
Application: 08/131,541 →
Reset Signal Generation Circuit Having a Function for Protecting Write Data
Patent: 5,457,660 →
Application: 08/131,818 →
Bandpass Sigma-Delta Analog-to-Digital Converter (Adc), Method Therefor, and Receiver Using Same
Patent: 5,442,353 →
Application: 08/140,948 →
Method of Cell Characterization for Energy Dissipation
Patent: 5,504,694 →
Application: 08/141,368 →
Method and Apparatus for Integrating a Plurality of Analog Input Signals Prior to Transmitting a Communications Signal
Patent: 5,634,202 →
Application: 08/149,486 →
Method and Apparatus for Performing Read Accesses from a Counter Which Avoid Large Rollover Error When Multiple Read Access Cycles Are Used
Patent: 5,566,322 →
Application: 08/154,774 →
Electronic Device Having Coplanar Heatsink and Electrical Contacts
Patent: 5,457,605 →
Application: 08/155,879 →
Integrated Circuit Having an on Chip Thermal Circuit Requiring Only One Dedicated Integrated Circuit Pin and Method of Operation
Patent: 5,376,819 →
Application: 08/158,323 →
Method and Apparatus for Performing Parallel Zero Detection in a Data Processing System
Patent: 5,367,477 →
Application: 08/158,326 →
Method and Apparatus for Performing Multiplexed and Non-Multiplexed Bus Cycles in a Data Processing System
Patent: 5,483,660 →
Application: 08/158,584 →
Auto-Calibrated Current-Mode Digital-to-Analog Converter and Method Therefor
Patent: 5,446,455 →
Application: 08/160,645 →
Method and Apparatus for Performing Frequency Tracking in an All Digital Phase Lock Loop
Patent: 5,381,116 →
Application: 08/165,682 →
Filtering Device for Use in a Phase Locked Loop Controller
Patent: 5,424,689 →
Application: 08/172,000 →
Process for Measuring Surface Topography Using Atomic Force Microscopy
Patent: 5,383,354 →
Application: 08/172,974 →
Artificial Neuron Using Adder Circuit and Method of Using Same
Patent: 5,548,685 →
Application: 08/176,604 →
Circuit and Method of Zero Generation in a Real-Time Filter
Patent: 5,394,036 →
Application: 08/176,971 →
Printed Circuit Board Comprising Elevated Bond Pads
Patent: 5,523,920 →
Application: 08/176,992 →
Single Metal-Plate Bypass Capacitor
Patent: 5,377,072 →
Application: 08/179,275 →
Method for Thinning a Semiconductor Wafer
Patent: 5,476,566 →
Application: 08/187,363 →
Two's Complement Pulse Width Modulator and Method for Pulse Width Modulating a Two's Complement Number
Patent: 5,428,639 →
Application: 08/202,060 →
Adjustable Plating Cell for Uniform Bump Plating of Semiconductor Wafers
Patent: 5,391,285 →
Application: 08/202,210 →
High Speed Adder Using a Varied Carry Scheme and Related Method
Patent: 5,375,081 →
Application: 08/206,288 →
Pipelined Memory Having Synchronous and Asynchronous Operating Modes
Patent: 5,384,737 →
Application: 08/207,509 →
Circuit for Providing a Voltage Ramp Signal
Patent: 5,502,410 →
Application: 08/212,750 →
Circuit and Method for Enhancing Logic Transitions Appearing on a Line
Patent: 5,510,739 →
Application: 08/218,283 →
A Method of Forming a Ferromgnetic Memory Device
Patent: 5,389,566 →
Application: 08/218,395 →
Methods for Making and Using a Shallow Semiconductor Junction
Patent: 5,384,269 →
Application: 08/221,546 →
Comparator Having Latched Output When Disabled from the Power Supply
Patent: 5,488,320 →
Application: 08/223,400 →
A Power Circuit Package
Patent: 5,508,559 →
Application: 08/233,100 →
Electronic Module for Removing Heat from a Semiconductor Die
Patent: 5,565,705 →
Application: 08/235,992 →
Method for Connection of Signals to an Integrated Circuit
Patent: 5,501,006 →
Application: 08/239,796 →
Latching Ecl to Cmos Input Buffer Circuit
Patent: 5,426,381 →
Application: 08/247,819 →
Method for Coupling a Power Lead to a Bond Pad in an Electronic Module
Patent: 5,544,412 →
Application: 08/247,944 →
Antenna and Method for Forming Same
Patent: 5,528,254 →
Application: 08/251,444 →
Power-On Reset Circuit for Preventing Multiple Word Line Selections During Power-Up of an Integrated Circuit Memory
Patent: 5,477,176 →
Application: 08/253,076 →
Circuit and Method of Jtag Testing Multichip Modules
Patent: 5,568,492 →
Application: 08/254,846 →
Method for Forming a Power Circuit Package
Patent: 5,371,043 →
Application: 08/255,533 →
Short Circuit Detector for Sensors
Patent: 5,483,817 →
Application: 08/257,263 →
Method for Forming a Carbon Doped Silicon Semiconductor Device Having a Narrowed Bandgap Charateristic
Patent: 5,441,901 →
Application: 08/257,972 →
Pressure Sensor Package for Reducing Stress-Induced Measurement Error
Patent: 5,438,877 →
Application: 08/258,889 →
Logic Circuit with Negative Differential Resistance Device
Patent: 5,477,169 →
Application: 08/261,799 →
Method of Forming a Probe for an Atomic Force Microscope
Patent: 5,388,323 →
Application: 08/263,117 →
Tuning Circuit for an Rc Filter
Patent: 5,625,316 →
Application: 08/269,509 →
Three Axes Accelerometer
Patent: 5,487,305 →
Application: 08/274,128 →
Data Processing System Having a Compensation Circuit for Compensating for Capacitive Coupling on a Bus
Patent: 5,555,513 →
Application: 08/282,404 →
Process for Fabricating an X-Ray Absorbing Mask
Patent: 5,464,711 →
Application: 08/283,325 →
Rotational Vibration Gyroscope
Patent: 5,511,419 →
Application: 08/283,342 →
Circuit and Method of Reducing Sidetone in a Receive Signal Path
Patent: 5,649,008 →
Application: 08/284,950 →
An Interconnection Structure for Conductive Layers
Patent: 5,408,130 →
Application: 08/286,592 →
Method and Apparatus for Detecting Phase or Frequency Lock
Patent: 5,483,558 →
Application: 08/287,562 →
Flagless Semiconductor Device
Patent: 5,521,428 →
Application: 08/293,402 →
Method and Apparatus for Decoding Information Within a Processing Device
Patent: 5,530,659 →
Application: 08/297,479 →
Programmable Pin Configuration Logic Circuit for Providing a Chip Select Signal and Related Method
Patent: 5,511,182 →
Application: 08/298,638 →
Bus System Having a System Bus, an Internal Bus with Functional Units Coupled Therebetween and a Logic Unit for Use in Such System
Patent: 5,499,338 →
Application: 08/320,590 →
Integrated Circuit Data Processor Which Provides External Sensibility of Internal Signals During Reset
Patent: 5,574,894 →
Application: 08/333,658 →
Method and Apparatus for a Regulated Supply on an Integrated Circuit
Patent: 5,563,779 →
Application: 08/349,291 →
Method and Apparatus for Preventing a Data Processing System from Entering a Non-Recoverable State
Patent: 5,546,588 →
Application: 08/350,396 →
Amplifier Circuit Having High Lineraity for Cancelling Third Order Harmonic Distortion
Patent: 5,497,123 →
Application: 08/363,089 →
Data Processing System for Performing Efficient Fuzzy Logic Operations and Method Therefor
Patent: 5,671,332 →
Application: 08/363,196 →
Distributed Capacitance Transmission Line
Patent: 5,528,202 →
Application: 08/363,200 →
Optocoupler Package and Method for Making
Patent: 5,545,893 →
Application: 08/363,483 →
Microelectronic Device Packaging Containing a Liquid and Method
Patent: 5,477,084 →
Application: 08/367,628 →
Chemical-Mechanical-Polishing Pad Cleaning Process for Use During the Fabrication of Semiconductor Devices
Patent: 5,531,861 →
Application: 08/373,804 →
Method and Apparatus for Performing a Snoop-Retry Protocol in a Data Processing System
Patent: 5,506,971 →
Application: 08/386,252 →
Curvature Correction Circuit for a Voltage Reference
Patent: 5,479,092 →
Application: 08/388,116 →
Method of Processing a Semiconductor Chip Package
Patent: 5,690,877 →
Application: 08/405,563 →
Data Processor with Rename Buffer and Fifo Buffer for in-Order Instruction Completion
Patent: 5,500,943 →
Application: 08/442,913 →
Small Outline Optocoupler Package Method
Patent: 5,677,245 →
Application: 08/454,471 →
Apparatus for Comparing the Weight of a Binary Word to a Number
Patent: 5,623,519 →
Application: 08/591,191 →
Method of Requesting Data by Interlacing Critical and Non-Critical Data Words of Multiple Data Requests and Apparatus Therefor
Patent: 5,668,975 →
Application: 08/722,694 →
Apparatus and Method for Inserting an Address in a Data Stream Through a Fifo Buffer
Patent: 5,889,948 →
Application: 08/906,608 →
Address Generation Apparatus and Method Using a Peripheral Address Generation Unit and Fast Interrupts
Patent: 5,761,690 →
Application: 08/910,359 →
Related Assignments (4)
Other recorded transfers of the patents in this record — the chain of ownership.
Assignment of Assignor's Interest Jan 7, 2015
From: ZOZO MANAGEMENT, LLC
To: APPLE INC.
Reel/Frame 034732/0019 →
Patent Release Dec 21, 2015
From: CITIBANK, N.A., AS COLLATERAL AGENT
To: FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 037354/0225 →
Patent Release Dec 21, 2015
From: CITIBANK, N.A., AS COLLATERAL AGENT
To: FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 037356/0143 →
Patent Release Dec 21, 2015
From: CITIBANK, N.A., AS COLLATERAL AGENT
To: FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 037356/0553 →