Method for executing an instruction loop and a device having instruction loop execution capabilities
View Patent ↗A method for managing a hardware instruction loop, the method includes: (i) detecting, by a branch prediction unit, an instruction loop; wherein a size of the instruction loop exceeds a size of a storage space allocated in a fetch unit for storing fetched instructions; (ii) requesting from the fetch unit to fetch instructions of the instruction loop that follow the first instructions of the instruction loop; and (iii) selecting, during iterations of the instruction loop, whether to provide to a dispatch unit one of the first instructions of the instruction loop or another instruction that is fetched by the fetch unit; wherein the first instructions of the instruction loop are stored at the dispatch unit.
1. A method for executing an instruction loop, the method comprising:
in response to detecting, by a branch prediction unit, an instruction loop, wherein a size of the instruction loop exceeds a size of a storage space allocated in a fetch unit for storing fetched instructions:
storing, during a first iteration of the instruction loop, first instructions of the instruction loop at a dispatch unit;
maintaining storage of the first instructions at the dispatch unit between the first iteration and a subsequent set of iterations of the instruction loop;
during the first iteration and the subsequent set of iterations of the instruction loop, requesting from the fetch unit to fetch instructions of the instruction loop that follow the first instructions of the instruction loop;
selecting, during the subsequent set of iterations of the instruction loop, whether to provide from a dispatch unit one of the first instructions of the instruction loop stored at the dispatch unit or another instruction of the instruction loop that is fetched by the fetch unit; the another instruction not stored at the dispatch unit between the first iteration and the subsequent set of iterations of the instruction loop.
2. The method according to claim 1 wherein the stage of detecting is preceded by:
determining, by a controller, that an instruction loop is being processed by a pipeline stage of a processor; wherein during the determining the branch prediction unit is not aware that instructions that were fetched by the fetch unit form an instruction loop;
storing the first instructions of the instruction loop within the dispatch unit;
sending from the controller to the branch prediction unit instruction loop information;
requesting by the controller and from the fetch unit to fetch instructions of the instruction loop that follow the first instructions of the instruction loop.
3. The method according to claim 2 comprising determining by the controller that an instruction loop is being processed in response to a retrieval of an instruction loop indicator by the controller.
4. The method according to claim 2 wherein maintaining storage of the first instructions comprises preventing an erasure of the first instructions from the dispatch unit during the loop.
5. The method according to claim 1 wherein storing the first instructions comprises storing the first two instructions of the instruction loop within the dispatch unit and wherein the another instruction of the instruction loop.
6. The method according to claim 1 comprising storing first variable length groups of instructions of the instruction loop within the dispatch unit and requesting from the fetch unit to fetch other variable length groups of instructions of the instruction loop.
7. The method according to claim 1 comprising storing first fixed size fetch sets of the instruction loop within the dispatch unit and requesting from the fetch unit to fetch other variable length groups of instructions of the instruction loop.
8. The method according to claim 1 comprising storing first two fixed size fetch sets of the instruction loop within the dispatch unit and requesting from the fetch unit to fetch other variable length groups of instructions of the instruction loop.
9. A system for executing an instruction loop, the system comprising:
a fetch unit, configured to fetch instructions from a memory unit;
a branch prediction unit that is configured to:
in response to detecting an instruction loop, wherein a size of the instruction loop exceeds a size of a storage space allocated in the fetch unit for storing fetched instructions:
store, during a first iteration of the instruction loop, first instructions of the instruction loop at a dispatch unit;
maintain storage of the first instructions at the dispatch unit between the first iteration and a subsequent set of iterations of the instruction loop;
during the first iteration and the subsequent set of iterations of the instruction loop, request from the fetch unit to fetch instructions of the instruction loop that follow the first instructions of the instruction loop; and
select, during iterations of the instruction loop, whether to provide from a dispatch unit one of the first instructions of the instruction loop or another instruction of the instruction loop that is fetched by the fetch unit; wherein the another instruction is not stored at the dispatch unit between the first iteration and the subsequent iterations of the instruction loop.
10. The system according to claim 9 further comprising a controller that is configured to:
determine that an instruction loop is being processed by a pipeline stage of a processor; wherein during the determining the branch prediction unit is not aware that instructions that were fetched by the fetch unit form an instruction loop; storing the first instructions of the instruction loop within the dispatch unit;
send to the branch prediction unit instruction loop information;
request from the fetch unit to fetch instructions of the instruction loop that follow the first instructions of the instruction loop.
11. The system according to claim 9 wherein the controller is configured to determine that an instruction loop is being processed in response to a retrieval of an instruction loop indicator.
12. The system according to claim 9 wherein the dispatch unit erases the first instructions of the instruction loop after a completion of an iteration sequence of the instruction loop while the branch prediction unit stores the instruction loop information after the completion of the iteration sequence of the instruction loop.
13. The system according to claim 9 wherein the dispatch unit stores the first two instructions of the instruction loop and the branch prediction unit requests from the fetch unit to fetch the third instruction of the instruction loop and additional instructions that follow the third instructions of the instruction loop.
14. The system according to claim 9 wherein the dispatch unit stores first variable length groups of instructions of the instruction loop and the branch prediction unit requests from the fetch unit to fetch other variable length groups of instructions of the instruction loop.
15. The system according to claim 9 wherein the dispatch unit stores first two variable length groups of instructions of the instruction loop and the branch prediction unit requests from the fetch unit to fetch other variable length groups of instructions of the instruction loop.
16. The system according to claim 9 wherein the dispatch unit stores first fixed size fetch sets of the instruction loop and the branch prediction unit requests from the fetch unit to fetch other variable length groups of instructions of the instruction loop.
17. The system according to claim 9 wherein the dispatch unit stores first two fixed size fetch sets of instructions of the instruction loop and the branch prediction unit requests from the fetch unit to fetch other variable length groups of instructions of the instruction loop.
18. The system according to claim 9 , further comprising a processor core, the processor core comprising the fetch unit.
19. The system according to claim 18 , wherein the processor core comprises a digital signal processor core.
20. The system according to claim 9 , further comprising a plurality of processor cores, the plurality of processor cores including the fetch unit.