Electronic device having a memory element and method of operation therefor
View Patent ↗An electronic device comprises a processing unit operably coupled to a buffer random access memory, in turn operably coupled to a non-volatile memory configured to emulate an electrically erasable programmable read only memory. The processing unit is arranged to transfer data between the buffer RAM and the non-volatile memory at a first clock frequency. A second RAM is operably coupled between the processing unit and the non-volatile memory and the processing unit sets a Tag bit in the second RAM to identify an address in the buffer RAM that is being written to or read from by the processing unit.
1. An electronic device comprising
a processing unit operably coupled to a buffer random access memory, in turn operably coupled to a non-volatile memory configured to emulate an electrically erasable programmable read only memory, wherein the processing unit is arranged to transfer data between the buffer RAM and the non-volatile memory at a first clock frequency; and
a second RAM is operably coupled between the processing unit and the non-volatile memory and the processing unit sets a Tag bit in the second RAM to identify an address in the buffer RAM that is being written to or read from by the processing unit, wherein the second RAM is provided with a second clock frequency that is a multiple of the first clock frequency wherein the second RAM identifies an address of the data in the buffer RAM to be transferred to/from the non-volatile memory.
2. The electronic device of claim 1 wherein the processing unit is configured to set the Tag bit in the second RAM within a single cycle access time of the buffer RAM through use of the second clock frequency.
3. The electronic device of claim 1 further comprising data handler logic located between the buffer RAM and the non-volatile memory.
4. The electronic device of claim 3 wherein the processing unit clears the Tag bit in the second RAM when the buffer RAM is read from or written to by the data handler logic.
5. The electronic device of claim 1 , by further comprising a counter operably coupled to the processing unit, the buffer RAM and the second RAM and the processing unit increments or decrements the counter to identify when a respective read or write operation is to be performed by the buffer RAM.
6. The electronic device of claim 1 wherein the processing unit operates in a real-time multi-tasking system.
7. The electronic device of claim 1 wherein the second RAM and the buffer RAM employ a one-to-one mapping between a number of addresses therein.
8. The electronic device of claim 1 wherein the second RAM and the buffer RAM employ a one-to-one mapping between substantially all of the addresses therein.
9. A method of reading data from or writing data to a non-volatile memory configured to emulate an electrically erasable programmable read only memory, via a buffer random access memory comprising:
transferring data between the buffer RAM and the non-volatile memory at a first clock frequency;
providing a second RAM operably coupled to the non-volatile memory;
setting a Tag bit in the second RAM that identifies an address in the buffer RAM that is being written to or read from by the processing unit;
providing the second RAM with a second clock frequency that is a multiple of the first clock frequency; and
identifying, in the second RAM, an address of the data in the buffer RAM to be transferred to/from the non-volatile memory.
10. The method of claim 9 further comprising setting the Tag bit in the second RAM within a single cycle access time of the buffer RAM through use of the second clock frequency.
11. The method of claim 10 further comprising clearing the Tag bit in the second RAM in response to the buffer RAM being read from or written to.
12. The method of claim 10 , further comprising incrementing or decrementing a counter operably coupled to the buffer RAM and the second RAM to identify when a respective read or write operation is to be performed by the buffer RAM.
13. The method of claim 10 , further comprising employing a one-to-one mapping between a number of addresses in the second RAM and the buffer RAM.
14. The method of claim 9 further comprising clearing the Tag bit in the second RAM in response to the buffer RAM being read from or written to.
15. The method of claim 14 further comprising setting the Tag bit in the second RAM within a single cycle access time of the buffer RAM through use of the second clock frequency.
16. The method of claim 9 , further comprising incrementing or decrementing a counter operably coupled to the buffer RAM and the second RAM to identify when a respective read or write operation is to be performed by the buffer RAM.
17. The method of claim 9 , further comprising employing a one-to-one mapping between a number of addresses in the second RAM and the buffer RAM.
18. The method of claim 9 , further comprising employing a one-to-one mapping between substantially all of the addresses between the second RAM and the buffer RAM.
19. A method of reading data from or writing data to a non-volatile memory configured to emulate an electrically erasable programmable read only memory, via a buffer random access memory comprising:
transferring data between the buffer RAM and the non-volatile memory at a first clock frequency;
providing a second RAM operably coupled to the non-volatile memory;
setting a Tag bit in the second RAM that identifies an address in the buffer RAM that is being written to or read from by the processing unit; and
setting the Tag bit in the second RAM within a single cycle access time of the buffer RAM through use of the second clock frequency.
20. The method of claim 19 further comprising clearing the Tag bit in the second RAM in response to the buffer RAM being read from or written to.