Debug trace messaging with one or more characteristic indicators
View Patent ↗In a data processing system, an address associated with a processing operation is received. A modified address is generated which includes a characteristic indicator within the address at a first predetermined bit position when the characteristic indicator is of a first type or at a second predetermined bit position when the characteristic indicator is of a second type. A first value of the characteristic indicator indicates a characteristic of the address. A modified address may also be generated which includes a characteristic indicator at a first predetermined bit position when a position indicator has a first value or at a second predetermined bit position when the position indicator has a second value. Address information can then be generated from the modified address, and a debug message can be created which includes the address information.
1. A method for generating a debug message in a data processing system, the method comprising:
receiving an address associated with a processor operation;
generating a modified address by modifying the address to include a characteristic indicator within the address at a first predetermined bit position when the characteristic indicator is of a first type or at a second predetermined bit position, different from the first predetermined bit position, when the characteristic indicator is of a second type, the characteristic indicator having a first value which indicates a characteristic of the address;
generating address information from the modified address; and
creating a debug message which includes the address information.
2. The method of claim 1 , wherein the generating the address information comprises:
modifying a previous address associated with a previous processor operation to include the characteristic indicator at a same predetermined bit position as in the modified address to generate a modified previous address, the characteristic indicator having a second value which indicates a characteristic of the previous address; and
using the modified previous address and the modified address to generate the address information.
3. The method of claim 2 , wherein when the first value has a same value as the second value, the address information has a first length, and when the first value has a different value from the second value, the address information has a second length, different from the first length.
4. The method of claim 2 , wherein the using the modified previous address and the modified address to generate the address information comprises:
exclusive ORing the modified previous address and the modified address to generate the address information.
5. The method of claim 1 , wherein when the characteristic indicator is of the first type, the characteristic indicator indicates an instruction type associated with the address and when the characteristic indicator is of the second type, the characteristic indicator indicates an address type of the address.
6. The method of claim 5 , wherein the second predetermined bit position is a higher order bit position as compared to the first predetermined bit position.
7. The method of claim 5 , wherein when the characteristic indicator is of the second type, the first value of the characteristic indicator indicates whether the address is a logical or physical address.
8. The method of claim 1 , wherein when the characteristic indicator is of the first type, the address information has a different maximum length than when the characteristic indicator is of the second type.
9. A method for generating a debug message in a data processing system, the method comprising:
receiving an address associated with a processor operation;
determining a value of a position indicator;
determining a value of a characteristic indicator, wherein the value indicates a characteristic of the address;
when the position indicator has a first value, modifying the address to include the characteristic indicator at a first predetermined bit position within the address to generate a modified address;
when the position indicator has a second value, modifying the address to include the characteristic indicator at a second predetermined bit position with the address, different from the first predetermined bit position, to generate the modified address;
generating address information from the modified address; and
creating a debug message which includes the address information.
10. The method of claim 9 , wherein the generating the address information comprises:
modifying a previous address associated with a previous processor operation to include the characteristic indicator at a same predetermined bit position as in the modified address to generate a modified previous address, the characteristic indicator having a second value which indicates a characteristic of the previous address; and
using the modified previous address and the modified address to generate the address information.
11. The method of claim 10 , wherein when the first value has a same value as the second value, the address information has a first length, and when the first value has a different value from the second value, the address information has a second length, different from the first length.
12. The method of claim 10 , wherein the using the modified previous address and the modified address to generate the address information comprises:
exclusive ORing the modified previous address and the modified address to generate the address information.
13. The method of claim 9 , wherein the characteristic indicator indicates an address type of the address.
14. The method of claim 13 , wherein the value of the characteristic indicator indicates whether the address is a logical address or a physical address.
15. The method of claim 13 , wherein the first predetermined bit position is a higher order bit position as compared to the second predetermined bit position.
16. The method of claim 9 , wherein neither the first predetermined bit position nor the second predetermined bit position is a least significant bit position of the address.
17. A data processing system, comprising:
processing circuitry which performs processor operations; and
debug circuitry coupled to receive addresses from the processing circuitry associated with the processor operations and to provide debug messages using the addresses, wherein the debug circuitry comprises:
storage circuitry which stores a position indicator; and
message generation logic which modifies the addresses by including a characteristic indicator to generate modified addresses, wherein the characteristic indicator is placed at a first predetermined bit position of an address when the position indicator has a first value and the characteristic indicator is placed at a second predetermined bit position of the address when the position indicator has a second value, the message generation logic using the modified addresses to create debug messages which include address information.
18. The data processing system of claim 17 , wherein the message generation logic creates each of the debug messages by generating the address information from a previous modified address and a current modified address.
19. The data processing system of claim 18 , wherein the debug circuitry receives translated addresses and untranslated address from the processing circuitry, and wherein the characteristic indicator indicates whether the message generation logic generated the address information using a translated address or an untranslated address.
20. The data processing system of claim 17 , wherein the first predetermined bit position is a higher order bit position as compared to the second predetermined bit position.