Anneal of epitaxial layer in a semiconductor device
View Patent ↗An anneal of an epitaxially grown crystalline semiconductor layer comprising a combination of group-IV elements. The layer contains at least one of the group of carbon and tin. The layer of epitaxially grown material is annealed at a temperature substantially in a range of 1,000 to 1,400 degrees Celsius for a period not to exceed 100 milliseconds within 10% of the peak temperature. The anneal is performed for example with a laser anneal or a flash lamp anneal. The limited-time anneal may improve carrier mobility of a transistor.
1. A method comprising:
providing a semiconductor layer;
forming a layer of epitaxially grown crystalline material on the semiconductor layer using the semiconductor layer as a template layer, the layer of epitaxially grown crystalline material comprising a combination of group IV elements including at least one of a group of carbon and tin; and
annealing the layer of epitaxially grown crystalline material at a peak temperature in a range of approximately 1,000 to 1,400 degrees Celsius for a period not to exceed 100 milliseconds within 10% of the peak temperature.
2. The method of claim 1 wherein the annealing includes performing laser annealing.
3. The method of claim 1 wherein the annealing includes performing a flash lamp anneal.
4. The method of claim 1 wherein the layer of epitaxially grown crystalline material comprises carbon which has a first portion in interstitial form and a second portion in substitutional form, wherein the annealing converts interstitial form carbon to substitutional form to modify the layer of epitaxially grown crystalline material to have a substitutional carbon content of greater than two atomic percent.
5. The method of claim 1 further comprising:
in situ doping the layer of epitaxially grown crystalline material with an N-type dopant of at least one of a group of arsenic, phosphorous, nitrogen, and antimony.
6. The method of claim 1 further comprising:
in situ doping the layer of epitaxially grown crystalline material with a P-type dopant of at least one of a group of boron, aluminum, gallium, and indium.
7. The method of claim 1 wherein the combination of group IV elements includes one or more of a group consisting of silicon and geranium.
8. The method of claim 1 further comprising:
wherein the layer of epitaxially grown crystalline material includes at least a portion of a current terminal region of a transistor.
9. The method of claim 1 further comprising:
wherein the layer of epitaxially grown crystalline material includes at least a portion of a channel region of a transistor.
10. The method of claim 1 wherein the combination includes no more than twenty five atomic percent of a group consisting of carbon and tin.
11. The method of claim 1 wherein the annealing further includes annealing the layer of epitaxially grown crystalline material at a peak temperature in a range of approximately 1,000 to 1,400 degrees Celsius for a period not to exceed 10 milliseconds within 10% of the peak temperature.
12. A method comprising:
forming a transistor, the transistor having a current terminal region including at least a portion formed from a layer of epitaxially grown crystalline material, the layer of epitaxially grown crystalline material comprising silicon and carbon; and
annealing the layer of epitaxially grown crystalline material at a peak temperature in a range of approximately 1,000 to 1,400 degrees Celsius for a period not to exceed 100 milliseconds within 10% of the peak temperature.
13. The method of claim 12 further comprising:
in situ doping the layer of epitaxially grown crystalline material with an N-type dopant of at least one of a group of nitrogen, phosphorus, arsenic, or antimony.
14. The method of claim 12 wherein the annealing functions as a primary activation method to activate dopants into the current terminal region of the transistor.
15. The method of claim 12 wherein the layer of epitaxially grown crystalline material is formed over a semiconductor layer, the method further comprising:
etching a region of the semiconductor layer to remove some but not all of a semiconductor material in the region;
forming the epitaxially grown crystalline material in the region where some of the semiconductor material was removed.
16. The method of claim 12 wherein the annealing the layer of epitaxially grown crystalline material includes performing laser annealing.
17. The method of claim 12 wherein the annealing includes performing a flash lamp anneal.
18. The method of claim 12 wherein a first portion of the carbon in the layer of epitaxially grown crystalline material is in interstitial form and a second portion of the carbon in the layer of epitaxially grown crystalline material is in substitutional form, wherein the annealing converts interstitial form of carbon to substitutional form to modify the layer of epitaxially grown crystalline material to have a substitutional carbon content of greater than two atomic percent.
19. The method of claim 12 wherein the annealing further includes annealing the layer of epitaxially grown crystalline material at a peak temperature in a range of approximately 1,000 to 1,400 degrees Celsius for a period not to exceed 10 milliseconds within 10% of the peak temperature.
20. The method of claim 12 wherein a at least a portion of a channel region of the transistor is located in the layer of epitaxially grown crystalline material.
21. A method comprising:
forming a P-channel transistor, the transistor having a channel region including at least a portion formed from a layer of epitaxially grown material comprising at least one of a group of silicon and germanium and further comprising at least one of a group of tin and carbon; and
annealing the layer of epitaxially grown material at a peak temperature in a range of approximately 1,000 to 1,400 degrees Celsius for a period not to exceed 100 milliseconds within 10% of the peak temperature.
22. The method of claim 21 further comprising:
in situ doping the layer of epitaxially grown material with a P-type dopant of at least one of boron, indium, aluminum and gallium.
23. The method of claim 21 wherein the annealing the layer of epitaxially grown material includes laser annealing.
24. The method of claim 21 further comprising:
the annealing the layer of epitaxially grown material includes flash lamp annealing.
25. The method of claim 21 wherein the annealing includes annealing the layer of epitaxially grown material at a peak temperature in a range of approximately 1,000 to 1,400 degrees Celsius for a period not to exceed 10 milliseconds within 10% of the peak temperature.
26. A method comprising:
forming an N-channel transistor, the transistor having a channel region, wherein at least a portion of the channel region is formed from a layer of epitaxially grown material comprising silicon and carbon; and
annealing the layer of epitaxially grown material at a peak temperature in a range of approximately 1,000 to 1,400 degrees Celsius for a period not to exceed 100 milliseconds within 10% of the peak temperature.