Communication steering for use in a multi-master shared resource system
View Patent ↗New approaches for providing communication between multiple masters ( 12, 14 ) and one or more shared resources ( 24, 30, 100 ) are needed. One example of a resource that may need to be shared is circuitry complying with the Universal Serial Bus (USB) standard ( 100 ). The USB specification defines the use of USB endpoints as data and control channels that reside in a USB device. In some cases it is desirable to have a certain number of endpoints controlled by one processor, and other endpoints controlled by a different processor, thus providing a shared control of all the endpoints. Circuitry ( 402, 417, 480 ) may be used to provide steering for additional signals such as interrupts. Other shared resources ( 24, 30 ) may use more centralized circuitry ( 36 ) to perform a steering function for additional signals.
1. Circuitry comprising:
a bus interface which communicates with a first master and a second master;
endpoint storage circuitry, coupled to the bus interface, the endpoint storage circuitry comprising a plurality of data endpoints wherein each of the plurality of data endpoints is allocatable to one of the first master and the second master;
a serial interface engine which communicates with a USB host;
a USB function controller, coupled to the bus interface, endpoint storage circuitry, and serial interface engine, the USB function controller comprising:
USB protocol logic, coupled to the serial interface engine;
endpoint interrupt logic which generates interrupts based on information received from the USB protocol logic;
interrupt steering registers, accessible by both the first master and the second master; and
interrupt steering logic which routes each of the interrupts to a corresponding one of the first master and the second master based on steering information provided by the interrupt steering registers; and
a resource ownership register, coupled to the first master and the second master, the resource ownership register allowing the first master to control a control endpoint under a first condition and allowing the second master to control the control endpoint under a second condition,
wherein the first master and the second master are not USB hosts.
2. Circuitry as in claim 1 , wherein the plurality of data endpoints are allocated based on the interrupt steering registers.
3. Circuitry as in claim 2 , wherein, for each of the plurality of data endpoints, the interrupt steering registers indicate allocation to one of the first master and the second master.
4. Circuitry as in claim 2 , wherein the interrupt steering registers comprise an interrupt steering set register and an interrupt steering clear register.
5. Circuitry as in claim 4 , wherein the interrupt steering registers further comprise interrupt steering storage circuitry coupled to the interrupt steering set register and the interrupt steering clear register, the interrupt steering storage circuitry providing the steering information to the interrupt steering logic.
6. Circuitry as in claim 5 , wherein the interrupt steering storage circuitry comprises a plurality of set-reset latches.
7. Circuitry comprising:
a plurality of data endpoints wherein each of the plurality of endpoints is allocatable to one of a plurality of bus masters, wherein the plurality of bus masters are not USB hosts;
a control endpoint wherein the control endpoint is allocated to a first one of the plurality of bus masters under a first condition, and wherein the control endpoint is allocated to a second one of the plurality of bus masters under a second condition;
a USB function controller, coupled to the plurality of endpoints, the USB function controller comprising:
endpoint interrupt logic which generates interrupts based on communication from a USB host;
at least one interrupt steering register accessible by the plurality of bus masters; and
interrupt steering logic which routes each of the interrupts to a corresponding bus master of the plurality of bus masters based on steering information provided by the interrupt steering registers.
8. Circuitry as in claim 7 , wherein the at least one interrupt steering register comprises an interrupt steering set register and an interrupt steering clear register.
9. Circuitry as in claim 8 , wherein the at least one interrupt steering registers further comprise interrupt steering storage circuitry coupled to the interrupt steering set register and the interrupt steering clear register, the interrupt steering storage circuitry providing the steering information to the interrupt steering logic.
10. A method, comprising:
providing a USB bus interface for communicating with a USB host;
providing a first bus master and a second bus master that are not USB hosts;
providing a plurality of USB endpoints wherein the plurality of USB endpoints comprise a control endpoint and a first data endpoint, wherein the control endpoint is allocated to the first bus master under a first condition and wherein the control endpoint is allocated to the second bus master under a second condition, and wherein the first data endpoint is allocated to the first bus master under a third condition and wherein the first data endpoint is allocated to the second bus master under a fourth condition;
providing an interrupt steering register that is modifyable by the first bus master and that is modifyable by the second bus master;
providing a mechanism to avoid corruption of contents of the interrupt steering register due to the interrupt steering register being modifyable by both the first bus master and by the second bus master;
using the interrupt steering register to determine if the first bus master is to receive an interrupt; and
using the interrupt steering register to determine if the second bus master is to receive the interrupt.
11. A method as in claim 10 , wherein the mechanism to avoid corruption of contents of the interrupt steering register comprises bitwise control of the interrupt steering register by the first bus master and the second bus master.
12. A method as in claim 10 , wherein the mechanism to avoid corruption of contents of the interrupt steering register comprises an atomic read-modify-write access.
13. A method as in claim 10 , wherein the plurality of USB endpoints reside in a USB device, the method further comprising:
if the USB device is unowned, allowing both the first bus master and the second bus master to access the interrupt steering register;
if the USB device is owned by the first bus master, allowing the first bus master and not the second bus master to access the interrupt steering register; and
if the USB device is owned by the second bus master, allowing the second bus master and not the first bus master to access the interrupt steering register.
14. A method as in claim 10 , wherein the first condition and the third condition are a reset condition.
15. A method as in claim 10 , wherein the plurality of USB endpoints reside in a USB device, the method further comprising:
forming the first bus master, the second bus master, and the interrupt steering register on a single integrated circuit,
wherein the first bus master has ownership of the USB device coming out of reset.
16. A method as in claim 10 , further comprising:
providing the interrupt steering register in the memory map/programmer's model.
17. A method as in claim 10 , wherein the step of providing an interrupt steering register comprises:
providing an interrupt steering set register; and
providing an interrupt steering clear register.
18. A method as in claim 10 , wherein each of the plurality of USB endpoints is allocatable to the first bus master under software control and is allocatable to the second bus master under software control.
19. A method as in claim 10 , wherein the plurality of USB endpoints comprise the first data endpoint and a second data endpoint, and wherein the first data endpoint can be allocated to the first bus master while the second data endpoint is allocated to the second bus master.
20. A method as in claim 10 , further comprising:
providing a non-USB bus interface for communicating with the first bus master and the second bus master;
providing a serial interface engine which communicates with the USB host by way of the USB bus interface;
providing USB protocol logic;
providing USB endpoint interrupt logic which generates interrupts based on information received from the USB protocol logic; and
providing interrupt steering logic which routes the interrupts based on steering information provided by the interrupt steering register.