Granted Patent B2

US 8,041,899 · App. 12/181,701 · Granted Oct 18, 2011

Abstract

Claims (32)

1. A write back allocate system, comprising:

a store request circuit;

a processor to generate a store request that comprises an information unit and an information unit address; and

a cache module, coupled to the store request circuit and to a high level memory unit; wherein a single cache module line comprises multiple segments, each segment to store a single information unit; wherein a content of a cache module line is retrieved from the high level memory unit by generating a fetch burst that comprises multiple segment fetch operations; and

wherein the store request circuit comprises a snooper and a controller;

wherein the snooper detects a portion of an address of a cache segment of a cache line that is being fetched during a fetch burst; and

wherein the controller is to request from the cache module to receive the information unit before a completion of the fetch burst if the portion of the address of the cache segment matches a corresponding portion of the information unit address and if the cache module declined a previous request to receive the information unit.

2. The write back allocate system according to claim 1 wherein the snooper detects a cache segment indicator that indicates which segment of the cache line is being fetched.

3. The write back allocate system according to claim 1 wherein the store request circuit comprises:

a declined buffer that stores store requests that are temporarily prevented from being written to the cache module; and

a pending buffer that stores store request before their eligibility to be written to the cache module is determined.

4. The write back allocate system according to claim 1 wherein the controller is to request from the cache module to receive, before the completion of the fetch burst, each store request that is stored in the store request module that has an information unit address portion that matches the portion of the address of the cache segment.

5. The write back allocate system according to claim 1 wherein the controller is to request from the cache module to receive, before the completion of the fetch burst, each head of buffer store request that has an information unit address portion that matches the portion of the address of the cache segment.

6. The write back allocate system according to claim 1 wherein the snooper detects a cache segment indicator that indicates which segment of the cache line is being fetched and wherein the controller is to request from the cache module to receive, before the completion of the fetch burst, each head of buffer store request that has an information unit address portion that matches the cache segment indicator.

7. The write back allocate system according to claim 1 wherein the snooper detects a cache segment indicator that indicates which segment of the cache line is being fetched and wherein the controller is to request from the cache module to receive, before the completion of the fetch burst, a head of pending buffer store request that has an information unit address portion that matches the cache segment indicator.

8. The write back allocate system according to claim 1 wherein the snooper detects a cache segment indicator that indicates which segment of the cache line is being fetched and wherein the controller is to request from the cache module to receive, before the completion of the fetch burst, a head of declined buffer store request that has an information unit address portion that matches the cache segment indicator.

9. The write back allocate system according to claim 1 wherein the controller is to request from the cache module to receive the information unit before the completion of the fetch burst if the portion of the address of the cache segment matches the corresponding portion of the information unit address, if the cache module declined the previous request to receive the information unit and if an address bus and a data bus of the cache module are idle.

10. A method for writing information units to a cache module, the method comprises:

storing, in an store request circuit, a store request that is generated by a processor, the store request comprises an information unit and an information unit address;

snooping, by the store request circuit, address lines that are coupled between a cache module and a high level memory to obtain a portion of an address of a cache segment of a cache line that is being retrieved during a burst of segment fetch operations; wherein each cache module line comprises multiple segments, each segment to store a single information unit; and

requesting from the cache module to receive the information unit before a completion of the fetch burst if the portion of the address of the cache segment matches a corresponding portion of the information unit address and if the cache declined a previous request to receive the information unit.

11. The method according to claim 10 comprising snooping address lines that convey a cache segment indicator that indicates which segment of the cache line is being fetched.

12. The method according to claim 10 comprising:

storing store requests that are temporarily prevented from being written to the cache module at a declined store request buffer; and

storing store request before their eligibility to be written to the cache module is determined, at a pending store request buffer.

13. The method according to claim 10 comprising requesting from the cache module to receive, before the completion of the fetch burst, each store request that is stored in the store request module that has an information unit address portion that matches the portion of the address of the cache segment.

14. The method according to claim 10 comprising requesting from the cache module to receive, before the completion of the fetch burst, each head of buffer store request that has an information unit address portion that matches the portion of the address of the cache segment.

15. The method according to claim 10 comprising detecting a cache segment indicator that indicates which segment of the cache line is being fetched and requesting from the cache module to receive, before the completion of the fetch burst, each head of buffer store request that has an information unit address portion that matches the cache segment indicator.

16. The method according to claim 10 comprising detecting a cache segment indicator that indicates which segment of the cache line is being fetched and requesting from the cache module to receive, before the completion of the fetch burst, a head of pending buffer store request that has an information unit address portion that matches the cache segment indicator.

17. The method according to claim 10 comprising detecting a cache segment indicator that indicates which segment of the cache line is being fetched and requesting from the cache module to receive, before the completion of the fetch burst, a head of declined buffer store request that has an information unit address portion that matches the cache segment indicator.

18. The method according to claim 10 comprising requesting from the cache module to receive the information unit before the completion of the fetch burst if the portion of the address of the cache segment matches the corresponding portion of the information unit address, if the cache declined the previous request to receive the information unit and if a cache module address bus and a cache module data bus are idle.

19. The method according to claim 10 comprising sending to a snooper a portion of the information unit address of a received store request circuit.

Assignments (17)