Transistor with gain variation compensation
View Patent ↗A semiconductor device and method of making comprises providing an active device region and an isolation region, the isolation region forming a boundary with the active device region. A patterned gate material overlies the active device region between first and second portions of the boundary. The patterned gate material defines a channel within the active device region, the gate material having a gate length dimension perpendicular to a centerline along a principal dimension of the gate material which is larger proximate the first and second portions of the boundary than in-between the first and second portions of the boundary. The channel includes a first end proximate the first portion of the boundary and a second end proximate the second portion of the boundary, further being characterized by gate length dimension tapering on both ends of the channel.
1. A semiconductor device comprising:
an active device region ( 12 );
an isolation region ( 14 ), wherein the isolation region forms a boundary ( 32 ) with the active device region; and
a patterned gate material ( 16 ) overlying the active device region between first and second portions of the boundary for defining a channel within the active device region, the patterned gate material having a gate length dimension perpendicular to a centerline along a principal dimension of the patterned gate material which is larger proximate the first and second portions of the boundary than in-between the first and second portions of the boundary.
2. The semiconductor device of claim 1 , wherein the channel includes a first end proximate the first portion of the boundary and a second end proximate the second portion of the boundary, the channel further being characterized by gate length dimension tapering on both ends of the channel.
3. The semiconductor device of claim 1 , wherein the gate length dimension perpendicular to the centerline proximate the first portion is symmetric about the centerline.
4. The semiconductor device of claim 1 , wherein the gate length dimension perpendicular to the centerline proximate the first portion is asymmetric about the centerline.
5. The semiconductor device of claim 1 , wherein the gate length dimension perpendicular to the centerline proximate the second portion is symmetric about the centerline.
6. The semiconductor device of claim 1 , wherein the gate length dimension perpendicular to the centerline proximate the second portion is asymmetric about the centerline.
7. The semiconductor device of claim 1 , wherein the gate length dimension perpendicular to the centerline (i) proximate the first portion is symmetric about the centerline and (ii) proximate the second portion is symmetric about the centerline.
8. The semiconductor device of claim 1 , wherein the gate length dimension perpendicular to the centerline (i) proximate the first portion is asymmetric about the centerline and (ii) proximate the second portion is asymmetric about the centerline.
9. The semiconductor device of claim 1 , wherein the isolation region comprises a shallow trench isolation region.
10. The semiconductor device of claim 1 , wherein the patterned gate material comprises one of a group consisting of polysilicon and metal.
11. The semiconductor device of claim 1 , wherein short channel effects proximate the first and second portions of the boundary are reduced in response to a larger gate length dimension at ends of the channel as compared to short channel effects in-between the first and second portions of the boundary.
12. The semiconductor device of claim 1 , wherein the channel includes a channel width between the first and second portions of the boundary and wherein an undesirable current density magnitude effect extends from at least one end of the channel inwardly at a maximum distance on the order of between thirty to fifty percent (30-50%) of the channel width.
13. The semiconductor device of claim 12 , further wherein the channel width is about 100 nm and the undesirable current density magnitude effect extends from at least one end of the channel inwardly between about 30 to 50 nm.
14. A semiconductor device comprising:
an active device region;
an isolation region, wherein the isolation region forms a boundary with the active device region; and
a patterned gate material overlying the active device region between first and second portions of the boundary for defining a channel within the active device region, the patterned gate material having a gate length dimension perpendicular to a centerline along a principal dimension of the gate material which is larger proximate the first and second portions of the boundary than in-between the first and second portions of the boundary,
wherein the channel includes a first end proximate the first portion of the boundary and a second end proximate the second portion of the boundary, the channel further being characterized by gate length dimension tapering on both ends of the channel,
wherein the gate length dimension perpendicular to the centerline proximate the first portion is one of symmetric and asymmetric about the centerline, and
wherein the gate length dimension perpendicular to the centerline proximate the second portion is one of symmetric and asymmetric about the centerline.
15. A method of making a semiconductor device comprising:
forming an isolation region about an active device region; and
patterning a gate material overlying the isolation and active device regions, wherein patterning includes patterning the gate material to result in a patterned gate material having a principal dimension overlying at least the active device region between first and second portions of a boundary that defines a channel within the active device region, the patterned gate material having a gate length dimension perpendicular to a centerline along the principal dimension of the patterned gate material which is larger proximate the first and second portions of the boundary than in-between the first and second portions of the boundary.
16. The method of claim 15 , wherein patterning the gate material further includes providing a mask with gate shape tapering features configured to produce the gate length dimension along the principal dimension of the patterned gate material in response to lithographically processing the gate material overlying the active device region using the mask.
17. The method of claim 16 , further wherein providing the mask with gate shape tapering features includes providing gate taper modulation features within a device layout for the semiconductor device, prior to an optical proximity correction processing, and prior to mask fabrication.
18. The method of claim 15 , wherein the channel includes a first end proximate the first portion of the boundary and a second end proximate the second portion of the boundary, the channel further being characterized by gate length dimension tapering on both ends of the channel.
19. The method of claim 15 , wherein the gate length dimension perpendicular to the centerline proximate the first portion is one of symmetric and asymmetric about the centerline, and wherein the gate length dimension perpendicular to the centerline proximate the second portion is one of symmetric and asymmetric about the centerline.
20. The method of claim 15 , wherein the isolation region comprises a shallow trench isolation, and wherein the gate material comprises one of a group consisting of polysilicon and metal.