System and method for arbitrating between memory access requests
View Patent ↗A system having memory access capabilities, the system includes: (i) a dynamic voltage and frequency scaling (DVFS) controller, adapted to determine a level of a voltage supply supplied to a first memory access requester and a frequency of a clock signal provided to the first memory access requester and to generate a DVFS indication that is indicative of the determination; (ii) a hardware access request determination module, adapted to determine a priority of memory access request issued by the first memory access requester in response to the DVFS indication; and (iii) a direct memory access arbitrator, adapted to arbitrate between memory access requests issued by the first memory access requester and another memory access requester in response to priorities associated with the memory access requests.
1. A system having memory access capabilities, comprising:
a dynamic voltage and frequency scaling (DVFS) controller, that determines a level of a voltage supply supplied to a first memory access requester and a frequency of a clock signal provided to the first memory access requester and generates a first DVFS indication that is indicative of the determination;
a hardware access request determination module that includes a plurality of sets of memory access request priorities, and that selects a first set of memory access request priorities of the plurality of sets of memory access request priorities in response to the first DVFS indication; and
a direct memory access arbitrator that arbitrates between memory access requests issued by the first memory access requester and a second memory access requester in response to the first set of memory access request priorities.
2. The system according to claim 1 wherein the hardware request determination module selects a second set of memory access request priorities of the plurality of sets of memory access request priorities, the second set of memory access request priorities having a reduced priority for memory access requests issued by the first memory access requester in response to an increment in the frequency of the clock signal provided to the first memory access requester.
3. The system according to claim 1 wherein the hardware request determination module selects a second set of memory access request priorities of the plurality of sets of memory access request priorities, the second set of memory access request priorities having an increased priority for memory access requests issued by the second memory access requester in response to an increment in the frequency of the clock signal provided to the first memory access requester.
4. The system according to claim 1 wherein the direct memory access arbitrator applies a weighted round robin arbitration algorithm that is responsive to the first set of memory access request priorities.
5. The system according to claim 1 wherein the first memory access requester is a graphical processing unit and the second memory access requester is a general purpose processing unit.
6. The system according to claim 1 wherein the first set of memory access request priorities is selected by the hardware access request determination module so as to optimize a utilization of a memory unit that is accessed by the direct memory access arbitrator.
7. The system according to claim 1 wherein;
the DVFS controller further determines a level of a voltage supply supplied to each memory access requester out of a group of memory access requesters and a frequency of each clock signal provided to each memory access requester out of a group of memory access requesters and generate a second DVFS indication that is indicative of the determinations; and
the hardware access request determination module further selects a second set of memory access request priorities in response to the second DVFS indication.
8. A method for accessing a memory unit, the method comprising:
determining, by a dynamic voltage and frequency scaling (DVFS) controller, a level of a voltage supply supplied to a first memory access requester and a frequency of a clock signal provided to the first memory access requester;
generating a first DVFS indication that is indicative of the determining;
selecting, by a hardware access request determination module a first set of memory access request priorities of a plurality of sets of memory access request priorities in response to the first DVFS indication; and
arbitrating, by a direct memory access arbitrator, between memory access requests issued by the first memory access requester and a second memory access requester in response to the first set of memory access request priorities.
9. The method according to claim 8 comprising selecting a second set of memory access request priorities of the plurality of sets of memory access request priorities, the second set of memory access request priorities having a reduced priority for memory access requests issued by the first memory access requester in response to an increment in the frequency of the clock signal provided to the first memory access requester.
10. The method according to claim 8 comprising selecting a second set of memory access request priorities, the second set of memory access request priorities having an increased priority for memory access requests issued by the second memory access requester in response to an increment in the frequency of the clock signal provided to the first memory access requester.
11. The method according to claim 8 comprising applying a weighted round robin arbitration algorithm that is responsive to the first set of memory access request priorities.
12. The method according to claim 8 wherein the first memory access requester is a graphical processing unit and the second memory access requester is a general purpose processing unit.
13. The method according to claim 8 , wherein the selecting the first set of memory access request priorities is done so as to optimize a utilization of a memory unit that is accessed.
14. The method according to claim 8 comprising:
determining a level of a voltage supply supplied to each memory access requestor out of a group of memory access requesters and a frequency of each clock signal provided to each memory access requester out of a group of memory access requesters;
generating a second DVFS indication that is indicative of the determinations; and
selecting a second set of memory access request priorities in response to the second DVFS indication.
15. A system having memory access capabilities, comprising:
a dynamic voltage and frequency scaling (DVFS) controller, that changes a first level of a voltage supply supplied to a first memory access requester of a plurality of memory access requesters and a first frequency of a clock signal provided to the first memory access requester and generates a first DVFS indication that is indicative of the change;
a hardware access request determination module, that:
selects a first set of priorities for memory access requests issued from the plurality of memory access requestors, wherein the first set of priorities is selected from a plurality of stored sets of priorities, and the first set of priorities includes a priority of the first memory access request, the selection being in response to the first DVFS indication; and
a direct memory access arbitrator, that arbitrates between the memory access requests included in the first set of priorities in response selecting the first set of priorities.
16. The system according to claim 15 wherein the hardware access request determination module selects a second set of priorities, the second set of priorities having a reduced priority for memory access requests issued by the first memory access requester in response to an increment in the frequency of the clock signal provided to the first memory access requester.
17. The system according to claim 15 wherein the hardware access request determination module selects a second set of priorities, the second set of priorities having an increased priority for second memory access requests issued by another memory access requester of the plurality of memory access requesters in response to an increment in the frequency of the clock signal provided to the first memory access requester.
18. The system according to claim 15 wherein;
the DVFS controller further determines a second level of a voltage supply supplied to a second memory access requester of the plurality of memory access requesters and a second frequency of a clock signal provided to the second memory access requester and generate a second DVFS indication that is indicative of the determinations; and
the hardware access request determination module further:
selects a second set of priorities of the plurality of sets of priorities for memory access requests issued from the plurality of memory access requestors, wherein the second set of priorities includes a priority of the second memory access request, the selection being in response to the second DVFS indication.
19. The system according to claim 15 , wherein the direct memory access arbitrator applies a weighted round robin arbitration algorithm that is responsive to the first set of priorities.
20. The system according to claim 15 , wherein the first memory access requester is a graphical processing unit.