Semiconductor resistor formed in metal gate stack
View Patent ↗A semiconductor process and apparatus fabricate a metal gate electrode ( 30 ) and an integrated semiconductor resistor ( 32 ) by forming a metal-based layer ( 26 ) and semiconductor layer ( 28 ) over a gate dielectric layer ( 24 ) and then selectively implanting the resistor semiconductor layer ( 28 ) in a resistor area ( 97 ) to create a conductive upper region ( 46 ) and a conduction barrier ( 47 ), thereby confining current flow in the resistor semiconductor layer ( 36 ) to only the top region ( 46 ) in the finally formed device.
1. A method for forming a resistor from a metal gate electrode stack, comprising:
providing a semiconductor substrate comprising a transistor area and a resistor area;
forming a gate dielectric layer over at least the transistor area;
forming a first metal-based layer over the transistor area and the resistor area;
depositing a semiconductor layer over the first metal-based layer;
patterning and etching the semiconductor layer and the first metal-based layer to form a metal gate electrode structure comprising a gate semiconductor layer over the transistor area and a resistor structure comprising a resistor semiconductor layer over the resistor area; and
forming a conduction barrier in a lower portion of the resistor semiconductor layer.
2. The method for forming a resistor from a metal gate electrode stack according to claim 1 wherein forming a gate dielectric layer comprises forming a high-k dielectric layer over at least the transistor area.
3. The method for forming a resistor from a metal gate electrode stack according to claim 1 wherein forming a first metal-based layer comprises depositing a thin layer of TiC, TiN, TaC, HfC, TaSi, ZrC or Hf.
4. The method for forming a resistor from a metal gate electrode stack according to claim 1 , where depositing a semiconductor layer comprises depositing a layer of silicon or silicon-germanium in an amorphous or polycrystalline state.
5. The method for forming a resistor from a metal gate electrode stack according to claim 1 , where forming the conduction barrier comprises implanting the resistor semiconductor layer with an extension implant that is used to form extension regions adjacent to the metal gate electrode structure so that an upper portion of the resistor semiconductor layer has a relatively high doping concentration and the lower portion of the resistor semiconductor layer has a relatively light doping concentration.
6. The method for forming a resistor from a metal gate electrode stack according to claim 1 , where forming the conduction barrier comprises:
in any order, forming an implantation barrier that covers the resistor semiconductor layer and exposes the transistor area, and forming implant spacers on sidewalls of at least the metal gate electrode structure; and then
implanting the resistor semiconductor layer with a source/drain implant that is used to form source/drain regions adjacent to the metal gate electrode structure so that an upper portion of the resistor semiconductor layer has a relatively high doping concentration and the lower portion of the resistor semiconductor layer has a relatively light doping concentration, where the source/drain implant implants the upper portion of the resistor semiconductor layer through the implantation barrier.
7. The method for forming a resistor from a metal gate electrode stack according to claim 6 , where forming an implantation barrier comprises depositing a silicon nitride layer over at least the resistor semiconductor layer to a thickness of approximately 150-250 Angstroms prior to implanting the resistor semiconductor layer with a source/drain implant.
8. The method for forming a resistor from a metal gate electrode stack according to claim 1 , where forming the conduction barrier comprises, in any order:
implanting first conductivity type impurities into an upper portion of the resistor semiconductor layer to form a first region having a relatively high doping concentration of the first conductivity type impurities; and
implanting second, opposite conductivity type impurities into a lower portion of the resistor semiconductor layer to form a second region having a relatively high doping concentration of the second conductivity type impurities,
where a P-N diode junction between the first and second regions forms the conduction barrier in the resistor semiconductor layer.
9. The method for forming a resistor from a metal gate electrode stack according to claim 1 , where forming the conduction barrier comprises, in any order:
forming an implant mask over the transistor area to protect the metal gate electrode structure; and
implanting first conductivity type impurities into an upper portion of the resistor semiconductor so that the upper portion of the resistor semiconductor layer has a relatively high doping concentration and the lower portion of the resistor semiconductor layer has a relatively light doping concentration.
10. The method for forming a resistor from a metal gate electrode stack according to claim 1 , where forming the conduction barrier comprises implanting impurities of a first conductivity type into an upper portion of the resistor semiconductor layer to form a conduction barrier in a lower portion of the resistor semiconductor layer.
11. The method for forming a resistor from a metal gate electrode stack according to claim 1 , where forming the conduction barrier comprises implanting impurities of a first conductivity type to counter-dope the lower portion of the resistor semiconductor layer to form a conduction barrier in the lower portion of the resistor semiconductor layer.
12. A method for simultaneously forming a metal gate and a semiconductor resistor, comprising:
providing a semiconductor substrate comprising at least one active surface region and a surface region of electrical isolation;
forming a dielectric layer on a surface of the semiconductor substrate;
forming a metallic layer over the dielectric layer;
forming a semiconductor layer over the metallic layer;
patterning and etching the semiconductor layer and the metallic layer to form a metal-semiconductor gate structure over the active surface region and a metal-semiconductor resistor structure over the surface region of electrical isolation; and
forming a conduction barrier in a lower portion of the semiconductor layer in the metal-semiconductor resistor structure.
13. The method for simultaneously forming a metal gate and a semiconductor resistor according to claim 12 , where forming a metallic layer over the dielectric layer comprises depositing a thin layer of TiC, TiN, TaC, HfC, TaSi, ZrC or Hf.
14. The method for simultaneously forming a metal gate and a semiconductor resistor according to claim 12 , where forming a semiconductor layer comprises depositing a layer of silicon or silicon-germanium in an amorphous or polycrystalline state.
15. The method for simultaneously forming a metal gate and a semiconductor resistor according to claim 12 , where forming the conduction barrier comprises implanting the metal-semiconductor resistor structure with an extension implant that is used to form extension regions adjacent to the metal-semiconductor gate structure so that an upper portion of the semiconductor layer in the metal-semiconductor resistor structure has a relatively high doping concentration and the lower portion of the resistor semiconductor layer has a significantly lower doping concentration.
16. The method for simultaneously forming a metal gate and a semiconductor resistor according to claim 12 , where forming the conduction barrier comprises:
selectively forming an implantation barrier over the metal-semiconductor resistor structure which provides a partial implantation block during a subsequent implantation; and then
implanting the metal-semiconductor resistor structure with an implant that is used to form source/drain regions adjacent to the metal-semiconductor gate structure so that an upper portion of the semiconductor layer in the metal-semiconductor resistor structure has a relatively high doping concentration and the lower portion of the semiconductor layer in the metal-semiconductor resistor structure has a relatively light doping concentration.
17. The method for simultaneously forming a metal gate and a semiconductor resistor according to claim 12 , where forming the conduction barrier comprises, in any order:
implanting first conductivity type impurities into an upper portion of the semiconductor layer in the metal-semiconductor resistor structure to form a first region having a relatively high doping concentration of the first conductivity type impurities; and
implanting second, opposite conductivity type impurities into a lower portion of the semiconductor layer in the metal-semiconductor resistor structure to form a second region having a relatively high doping concentration of the second conductivity type impurities,
where a P-N diode junction between the first and second regions forms the conduction barrier in the metal-semiconductor resistor structure.
18. The method for simultaneously forming a metal gate and a semiconductor resistor according to claim 12 , where forming the conduction barrier comprises, in any order:
forming an implant mask over the active surface region to protect the metal-semiconductor gate structure; and
implanting first conductivity type impurities into an upper portion of the semiconductor layer of the metal-semiconductor resistor structure so that the upper portion has a relatively high doping concentration and a lower portion of the semiconductor layer in the metal-semiconductor resistor structure has a relatively light doping concentration.
19. An integrated circuit, comprising:
a semiconductor substrate;
a metal-containing device structure formed over an active area of the semiconductor substrate comprising a first semiconductor layer formed over a first metal-based layer; and
a resistor structure formed over an isolation layer on the semiconductor substrate comprising a second semiconductor layer formed over a second metal-based layer, where the second semiconductor layer comprises a conduction barrier implemented with a difference in doping profile between an upper portion of the second semiconductor layer and a lower portion of the second semiconductor layer.
20. The integrated circuit of claim 19 , where the conduction barrier comprises impurities of a first conductivity type implanted in a lower portion of the second semiconductor layer and impurities of a second conductivity type implanted in an upper portion of the second semiconductor layer.