Methodology to reduce SOI floating-body effect
View Patent ↗A method for making a semiconductor device, comprising (a) providing a structure comprising a gate electrode ( 207 ) disposed on a substrate ( 203 ); (b) creating first ( 213 ) and second ( 214 ) pre-amorphization implant regions in the substrate such that the first and second pre-amorphization implant regions are asymmetrically disposed with respect to said gate electrode; (c) creating first ( 219 ) and second ( 220 ) spacer structures adjacent to first and second sides of the gate electrode, wherein the first and second spacer structures overlap the first and second pre-amorphization implant regions; and (d) creating source ( 217 ) and drain ( 218 ) regions in the substrate adjacent, respectively, to the first and second spacer structures.
1. A method for making a semiconductor device, comprising:
providing a structure comprising a gate electrode disposed on a substrate;
creating first and second pre-amorphization implant regions in the substrate such that the first and second pre-amorphization implant regions are asymmetrically disposed with respect to said gate electrode;
creating first and second extension regions in the substrate adjacent, respectively, to first and second sides of the gate electrode,
creating first and second spacer structures adjacent to first and second sides of the gate electrode such that the first and second spacer structures extend over the first and second pre-amorphization implant regions, respectively;
creating source and drain regions in the substrate adjacent, respectively, to the first and second spacer structures; and
forming end of range defects in the substrate adjacent to the boundaries of the first and second pre-amorphization implant regions; wherein the first and second extension regions are created prior to the creation of the first and second spacer structures.
2. The method of claim 1 , wherein said first and second pre-amorphization implant regions are formed by implanting a first species at an angle φ, and wherein φ, as measured from an axis vertical to the substrate and in the direction of the source region, is within the range of about 20° to about 70°.
3. The method of claim 2 , wherein φ, as measured from an axis vertical to the substrate and in the direction of the source region, is within the range of about 30° to about 60°.
4. The method of claim 2 , wherein φ, as measured from an axis vertical to the substrate and in the direction of the source region, is within the range of about 40° to about 50°.
5. The method of claim 1 , further comprising:
creating a halo region in the substrate, wherein the halo region is created prior to the creation of the first and second spacer structures.
6. The method of claim 1 , wherein the first and second extension regions are disposed asymmetrically about the gate electrode.
7. The method of claim 1 , wherein the halo region comprises a first halo region disposed adjacent to the first extension region and a second halo region disposed adjacent to the second extension region, and wherein the first and second halo regions are disposed asymmetrically about the gate electrode.
8. The method of claim 1 , wherein said first and second extension regions are formed by implanting a second species at an angle σ 1 , and wherein σ 1 , as measured from an axis vertical to the substrate and in the direction of the source region, is within the range of about 5° to about 45°.
9. The method of claim 1 , wherein said first and second extension regions are formed by implanting a second species at an angle σ 1 , and wherein σ 1 , as measured from an axis vertical to the substrate and in the direction of the source region, is within the range of about 10° to about 30°.
10. The method of claim 1 , wherein said first and second extension regions are formed by implanting a second species at an angle σ 1 , and wherein σ 1 , as measured from an axis vertical to the substrate and in the direction of the source region, is within the range of about 10° to about 20°.
11. The method of claim 1 , wherein the first and second extension regions have a first conductivity type, and wherein the halo region has a second conductivity type that is opposite to the first conductivity type.
12. The method of claim 1 , further comprising annealing the structure such that end of range defects are created in the substrate.
13. The method of claim 12 , wherein the end of range defects are formed along first and second axes which are asymmetrically disposed about the gate electrode.
14. The method of claim 1 , wherein the first and second pre-amorphozation implant regions are created by implanting a species selected from the group consisting of Si, Ge, Sb, In, As, P, BF 2 , Xe and Ar.
15. The method of claim 14 , wherein the first and second pre-amorphozation implant regions are created by implanting Ar.
16. The method of claim 1 , wherein the substrate is an SOI wafer.
17. The method of claim 16 , wherein the semiconductor device is a MOSFET.
18. The method of claim 1 , wherein the pre-amorphization regions are formed through implantation of a first dopant, wherein the source and drain regions are formed by implantation of a second dopant, and wherein the first and second dopants have opposite conductivities.
19. The method of claim 1 , further comprising:
creating third and fourth pre-amorphization implant regions in the substrate such that the first and second pre-amorphization implant regions are asymmetrically disposed with respect to said gate electrode.