SEMICONDUCTOR DEVICE AND METHOD OF MAKING SAME
In one example embodiment, an integrated semiconductor circuit ( 400 ) is provided. The integrated circuit ( 400 ) comprises a substrate ( 430 ) comprising a first material and a first electronic device ( 455 ) comprising a first depressed region ( 415 ) within the substrate ( 430 ) and a set of first device contact locations ( 475 ) in a contact level ( 300 ). The integrated circuit ( 400 ) further comprises a second electronic device 450 comprising a set of second device contact locations ( 451 ) in the contact level ( 300 ) and a second material ( 420 ) in the first depressed ( 415 ) region having a lattice mismatch with the first material.
1 . A transistor comprising:
a source component in a substrate;
a drain component in the substrate;
a channel formed between the source and the drain within a depressed region in the substrate;
a gate component in electrical communication with the channel;
wherein the substrate comprises a first material having a first lattice structure and the channel comprises a second material having a second lattice structure, wherein there is a lattice mismatch between the first and second lattice structures; and
wherein the channel comprises a substantially dislocation-free area of the depressed region.
2 . The transistor of claim 1 , wherein at least one of the source or the drain components comprises the first material.
3 . The transistor of claim 2 , wherein the at least one of the source or the drain components is substantially horizontally oriented with respect to the depressed region.
4 . The transistor of claim 1 , comprising a liner between at least a portion of the first material and at least a portion of the second material.
5 . The transistor of claim 1 , wherein the first material comprises Silicon.
6 . The transistor of claim 1 , wherein the second material comprises Germanium.
7 . The transistor of claim 1 , wherein the transistor is a MOSFET device.
8 . A transistor comprising:
an input component selected from the group consisting of a source and an emitter;
an output component selected from the group consisting of a collector and a drain;
a gain component selected from the group consisting of a channel and a base;
wherein the substrate comprises a first material having a first lattice structure and the gain component comprises a second material having a second lattice structure;
wherein there is a lattice mismatch between the first and the second lattice structures; and
wherein the gain component comprises a substantially dislocation-free area of the depressed region.
9 . The transistor of claim 8 further comprising a gate in electrical communication with the channel.
10 . The transistor of claim 8 wherein at least one of the input and the output components comprises the first material.
11 . The transistor of claim 8 wherein the at least one of the input and the output components is substantially horizontally oriented with respect to the depressed region.
12 . The transistor of claim 8 wherein the at least one of the input and the output components is substantially vertically oriented with respect to the depressed region.
13 . The transistor of claim 10 wherein the at least one of the input and the output components is substantially horizontally oriented with respect to the depressed region.
14 . The transistor of claim 10 wherein the at least one of the input and the output components is substantially vertically oriented with respect to the depressed region.
15 . The transistor of claim 8 , comprising a liner between at least a portion of the first material and at least a portion of the second material.
16 . The transistor of claim 8 wherein the first material comprises Silicon and the second material comprises Germanium.
17 . The transistor of claim 8 wherein the first material comprises Silicon.
18 . The transistor of claim 8 wherein the second material comprises Germanium.
19 . The transistor of claim 8 wherein the transistor is a bipolar device.
20 . The transistor of claim 8 wherein the transistor is a MOSFET.