Method for forming a split gate memory device
View Patent ↗A method forms a split gate memory device. A layer of select gate material over a substrate is patterned to form a first sidewall. A sacrificial spacer is formed adjacent to the first sidewall. Nanoclusters are formed over the substrate including on the sacrificial spacer. The sacrificial spacer is removed after the forming the layer of nanoclusters, wherein nanoclusters formed on the sacrificial spacer are removed and other nanoclusters remain. A layer of control gate material is formed over the substrate after the sacrificial spacer is removed. A control gate of a split gate memory device is formed from the layer of control gate material, wherein the control gate is located over remaining nanoclusters.
1. A method of forming a split gate memory device, the method comprising:
forming a layer of select gate material over a substrate;
patterning the layer of select gate material to form a first sidewall;
forming a sacrificial spacer adjacent to the first sidewall;
forming a layer of nanoclusters over the substrate including on the sacrificial spacer;
removing the sacrificial spacer after the forming the layer of nanoclusters, wherein the removing removes nanoclusters of the layer of nanoclusters formed on the sacrificial spacer and leaves other nanoclusters of the layer of nanoclusters;
forming a layer of control gate material over the substrate after the removing the sacrificial spacer; and
forming a control gate of a split gate memory device from the layer of control gate material, wherein the control gate is located over nanoclusters of the layer of nanoclusters.
2. The method of claim 1 further comprising:
forming a layer of dielectric material over the layer of nanoclusters after the removing of the sacrificial layer and prior to the forming the layer of control gate material.
3. The method of claim 1 further comprising:
forming a layer of dielectric material on the first sidewall prior to the forming the sacrificial spacer.
4. The method of claim 3 wherein the forming a layer of dielectric material on the first sidewall includes growing an oxide layer on the first sidewall by oxidizing material of the first sidewall.
5. The method of claim 3 wherein:
the forming a layer of dielectric material includes forming a layer of dielectric material over the substrate in a first area adjacent to the first sidewall and where the layer of select gate material has been removed;
the sacrificial spacer is formed in the first area on the layer of dielectric material;
the forming the layer of nanoclusters includes forming nanoclusters on the layer of dielectric material in a second area of the first area adjacent to the sacrificial spacer; and
removing the sacrificial spacer leaves nanoclusters of the layer of nanoclusters in the second area.
6. The method of claim 5 , wherein the split gate memory device includes a charge storage structure including nanoclusters of the layer of nanoclusters in the second area.
7. The method of claim 3 wherein the forming the sacrificial spacer includes forming a layer of spacer material on the layer of dielectric material.
8. The method of claim 3 wherein removing the sacrificial spacer includes etching the sacrificial spacer with an etch chemistry that is non selective to a material of the sacrificial spacer and does not etch a material of the layer of dielectric material.
9. The method of claim 1 wherein the forming a sacrificial spacer includes forming a sacrificial spacer that includes a nitride.
10. The method of claim 9 wherein the forming a sacrificial spacer includes forming a sacrificial spacer that includes titanium nitride.
11. The method claim 9 wherein the forming a sacrificial spacer includes forming a sacrificial spacer that includes silicon nitride.
12. The method of claim 1 wherein the forming a sacrificial spacer includes forming a sacrificial spacer that includes silicon germanium.
13. The method of claim 12 further comprising:
absorbing nanoclusters formed on the sacrificial spacer into the sacrificial spacer prior to the removing.
14. The method of claim 1 wherein the forming a sacrificial spacer includes forming a sacrificial spacer that includes amorphous carbon.
15. The method of claim 1 wherein the layer of nanoclusters include silicon.
16. The method of claim 1 wherein:
the patterning the layer of select gate material forms a second sidewall, the second sidewall is an opposite sidewall to the first sidewall; and
the first sidewall defines a first sidewall of a select gate of the split gate memory device and the second sidewall defines a second sidewall of the select gate.
17. The method of claim 1 wherein the control gate includes a base portion, wherein no nanoclusters of the layer of nanoclusters are located between the base portion and the first sidewall.
18. A method of forming a split gate memory device, the method comprising:
forming a first layer of dielectric material over a substrate;
forming a layer of select gate material over the first layer of dielectric material;
forming a select gate of a split gate memory device from the layer of select gate material wherein the forming a select gate includes patterning the layer of select gate material to form a first sidewall, wherein the patterning removes the layer of select gate material in a first area adjacent to the first sidewall;
forming a second dielectric layer on the first sidewall;
forming a sacrificial spacer on the second dielectric layer;
forming a layer of nanoclusters over the substrate including on the sacrificial spacer;
removing the sacrificial spacer with an etch chemistry that is selective to a material of the sacrificial spacer and does not etch a material of the second dielectric layer, wherein the removing removes nanoclusters of the layer of nanoclusters formed on the sacrificial spacer and leaves nanoclusters of the layer of nanoclusters formed in a second area of the first area outside a location of the sacrificial spacer, wherein a charge storage structure of the split gate memory device includes nanoclusters of the layer of nanoclusters in the second area;
forming a layer of control gate material over the substrate after the removing of the sacrificial layer including over nanoclusters of the layer of nanoclusters in the second area; and
forming a control gate of the split gate memory device from the layer of control gate material.
19. A method of making a semiconductor device, the method comprising:
patterning a wafer to form a gate having a first sidewall and a lower surface in a first area adjacent to the first sidewall of the gate;
forming a first dielectric layer on the first sidewall of the gate and over the lower surface;
forming a sacrificial spacer on the first dielectric layer adjacent to the first sidewall of the gate in the first area, the sacrificial spacer having a lateral thickness that defines a laterally adjacent buffer zone of separation from the gate;
forming a layer of nanoclusters on the wafer including on the sacrificial spacer and over a second area of the first area located adjacent to the sacrificial spacer; and
removing the sacrificial spacer using an etch chemistry that is selective to a material of the sacrificial spacer and does not etch a material of the first dielectric layer, wherein the removing of the sacrificial spacer removes nanoclusters of the layer of nanoclusters formed on the sacrificial spacer and from the laterally adjacent buffer zone of separation from the gate and leaves nanoclusters of the layer of nanoclusters formed in the second area.
20. The method of claim 19 wherein forming the first dielectric layer comprises oxidizing material of the first sidewall and material of the lower surface.